Patents Assigned to Fuji Electric Device Technology Co., Ltd.
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Publication number: 20100025878Abstract: An imprinting method forms a pattern in a resist surface of a substrate coated with a thermoplastic resist by using a mold having a pattern of projections and recesses formed in a transfer surface. The method includes an alignment step, a heating step, a press step, a cooling step, and release step, wherein the steps are performed in a plurality of units selected from independent units, composite units, and combinations of independent units and composite units. A mold and a substrate are paired with each other and conveyed between the units. An imprinting apparatus includes a plurality of units which perform the steps in the imprinting method and which are selected from independent units, composite units, and combinations of independent units and composite units. Conveying devices are provided which convey the mold and the substrate paired with each other between the plurality of units.Type: ApplicationFiled: April 22, 2009Publication date: February 4, 2010Applicant: FUJI ELECTRIC DEVICE TECHNOLOGY CO., LTD.Inventor: Shinji UCHIDA
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Publication number: 20100029070Abstract: A method for producing a device includes embedding trenches with an epitaxial layer having high crystallinity while a mask oxide film remains unremoved. An n-type semiconductor is formed on the surface of a silicon substrate, and a mask oxide film and a mask nitride film are formed on the surface of the n-type semiconductor. The mask laminated film is opened by photolithography and etching, and trenches are formed in the silicon substrate. The width of the remaining mask laminated film is narrowed, whereby portions of the n-type semiconductor close to the opening ends of the trenches are exposed. The trenches are embedded with a p-type semiconductor, whereby the surface of the mask laminated film is prevented from being covered with the p-type semiconductor. The p-type semiconductor is grown from the second exposed portions of the n-type semiconductor. V-shaped grooves are prevented from forming on the surface of the p-type semiconductor.Type: ApplicationFiled: August 3, 2009Publication date: February 4, 2010Applicant: FUJI ELECTRIC DEVICE TECHNOLOGY CO., LTD.Inventor: Kazuya Yamaguchi
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Publication number: 20100027323Abstract: A magnetic recording element is disclosed for which current density required for writing is low and structure of the element is simple. It comprises a ferromagnetic fine wire formed on a Si substrate, current electrodes that contact ends of the ferromagnetic fine wire, and voltage electrodes joined to the ferromagnetic fine wire and current electrodes to measure voltage across part of the ferromagnetic fine wire in cooperation with the current electrodes. A magnetic domain wall is induced in the ferromagnetic fine wire when the element is manufactured. A depression is formed in the surface on top of the ferromagnetic fine wire between the voltage electrodes, and between one of the current electrodes and one of the voltage electrodes. Voltage is measured between the two voltage electrodes when reading current is applied, to determine whether the magnetic domain wall is present between the two voltage electrodes, whereby recorded data can be identified.Type: ApplicationFiled: September 11, 2009Publication date: February 4, 2010Applicant: FUJI ELECTRIC DEVICE TECHNOLOGY CO., LTD.Inventor: Takuya ONO
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Publication number: 20100019342Abstract: In a semiconductor device having a pn-junction diode structure that includes anode diffusion region including edge area, anode electrode on anode diffusion region, and insulator film on edge area of anode diffusion region, the area of anode electrode above anode diffusion region with insulator film interposed between anode electrode and anode diffusion region is narrower than the area of insulator film on edge area of anode diffusion region.Type: ApplicationFiled: July 22, 2009Publication date: January 28, 2010Applicant: Fuji Electric Device Technology Co., Ltd.Inventors: Ryouichi KAWANO, Tomoyuki YAMAZAKI, Michio NEMOTO, Mituhiro KAKEFU
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Patent number: 7652861Abstract: An overcurrent detecting circuit and reference voltage circuit may reduce the current consumed by an electronic circuit. The circuit may includes a reference load through which a reference current flows, generating a reference voltage. A differential amplifier section is included to amplify the difference in the potentials of two inputs. At least part of a bias current supplied by a constant current source to the differential amplifier section flows to the reference load. A detection voltage, corresponding to a current subject to overcurrent detection, is inputted to one of the two inputs of the differential amplifier section.Type: GrantFiled: September 7, 2006Date of Patent: January 26, 2010Assignee: Fuji Electric Device Technology Co., Ltd.Inventor: Kouhei Yamada
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Patent number: 7649746Abstract: A semiconductor device with an inductor device is small, thin, and low-cost. A laminated inductor is adhered fixedly onto a supporting conductive plate by Ag paste, and a semiconductor chip is adhered fixedly onto the laminated inductor via an insulating DAF tape. One end of the supporting conductive plate and a terminal electrode of the semiconductor chip are connected by a metal wire, and a plurality of terminal electrodes of the semiconductor chip and a plurality of external lead-out terminals are connected respectively by laterally extending metal wires. The entire structure is then sealed by a resin mold. By employing a laminated inductor and forming the metal wires to extend laterally in this manner, the thickness of the semiconductor device with an inductor can be reduced.Type: GrantFiled: February 2, 2007Date of Patent: January 19, 2010Assignee: Fuji Electric Device Technology Co., Ltd.Inventors: Osamu Hirohashi, Tomonori Seki
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Publication number: 20090323376Abstract: A semiconductor device incorporates a resistor on a structure that uses diffusion layers for sustaining the breakdown voltage thereof to realizes a very resistive element that exhibits a high breakdown voltage and high electrical resistance, includes a spiral very resistive element buried in an interlayer insulator film. A first end of the very resistive element is connected to a drain electrode wiring and the second end of the very resistive element is grounded. An intermediate point of the very resistive element is connected to ae voltage comparator of a control IC. The semiconductor device according to the invention facilitates reducing the components parts costs, assembly costs and size of a switching power supply that includes a very resistive element.Type: ApplicationFiled: August 4, 2009Publication date: December 31, 2009Applicant: FUJI ELECTRIC DEVICE TECHNOLOGY CO., LTD.Inventor: Masaru SAITO
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Publication number: 20090317959Abstract: A manufacturing method for manufacturing a super-junction semiconductor device forms an oxide film and a nitride film on an n-type epitaxial layer exhibiting high resistance on an n-type semiconductor substrate exhibiting low resistance. The portion of the nitride film in the scribe region is left unremoved by patterning and an alignment marker is opened through the nitride film. After opening a trench pattern in the oxide film, trenches having a high aspect ratio are formed. The portion of the oxide film outside the scribe region is removed and a p-type epitaxial layer is buried in the trenches. The overgrown p-type epitaxial layer is polished with reference to the nitride film, the polished surface is finished by etching, and the n-type epitaxial layer surface is exposed.Type: ApplicationFiled: June 23, 2009Publication date: December 24, 2009Applicant: FUJI ELECTRIC DEVICE TECHNOLOGY CO., LTD.Inventor: Manabu TAKEI
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Publication number: 20090317733Abstract: Disclosed is a compound having excellent electron transporting ability, which is useful for electrophotographic photosensitive bodies or organic EL devices. Specifically disclosed is a novel quinone compound having a structure represented by general formula (I). Also disclosed is a highly sensitive, positive charge type electrophotographic photosensitive body for copying machines and printers, wherein the novel organic material is used as a charge-transporting material in a photosensitive layer. Also specifically disclosed is an electrophotographic photosensitive body having a photosensitive layer formed on a conductive base and containing a charge-generating material and a charge-transporting material, wherein the photosensitive layer contains at least one of the above-described compounds. Further disclosed is an electrophotographic apparatus using such a positive charge type electrophotographic photosensitive body.Type: ApplicationFiled: January 17, 2007Publication date: December 24, 2009Applicant: Fuji Electric Device Technology Co., Ltd.Inventors: Kenichi Okura, Yoichi Nakamura, Motohiro Takeshima, Yoshiki Hasegawa, Hiroyuki Kenmochi, Tohru Kobayashi
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Publication number: 20090315070Abstract: A power semiconductor device is provided, that realizes high-speed turnoff and soft switching at the same time, includes n-type main semiconductor layer including lightly doped n-type semiconductor layer and extremely lightly doped n-type semiconductor layer arranged alternately and repeatedly between p-type channel layer and field stop layer and in parallel to the first major surface of n-type main semiconductor layer. Extremely lightly doped n-type semiconductor layer is doped more lightly than lightly doped n-type semiconductor layer. Lightly doped n-type semiconductor layer prevents a space charge region from expanding at the time of turnoff. Extremely lightly doped n-type semiconductor layer expands the space charge region at the time of turnoff to eject electrons and holes quickly further to realize high-speed turnoff.Type: ApplicationFiled: May 15, 2009Publication date: December 24, 2009Applicant: FUJI ELECTRIC DEVICE TECHNOLOGY CO., LTD.Inventor: Koh Yoshikawa
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Patent number: 7635498Abstract: A perpendicular magnetic recording medium and method thereof, includes a nonmagnetic substrate; a soft magnetic under layer; an intermediate layer; a bilayer magnetic recording layer; a protective layer; and a liquid lubricant layer. According to a following order, the soft magnetic under layer, the intermediate layer, the bilayer magnetic recording layer, the protective layer, and the liquid lubricant layer are sequentially stacked on the nonmagnetic substrate. The bilayer magnetic recording layer includes a first magnetic layer including a CoCr alloy crystalline film, and a second magnetic layer including a rare earth-transition metal alloy noncrystalline film.Type: GrantFiled: April 27, 2005Date of Patent: December 22, 2009Assignee: Fuji Electric Device Technology, Co., Ltd.Inventors: Yasushi Sakai, Hiroyuki Uwazumi, Kazuo Enomoto, Sadayuki Watanabe
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Publication number: 20090309157Abstract: A MOS type semiconductor device, in which both improvement in radiation resistance and increase in withstand voltage is achieved, includes a nitride film formed on a LOCOS film and a PBSG film formed on the nitride film. The refractive index of the nitride film is set in a range of from 2.0 to 2.1 and the thickness of the nitride film is set in a range of from 0.1 Am to 0.5 ?m to thereby provide the nitride film as a semi-insulative thin film. Of electron-hole pairs produced in the LOCOS film by ?-ray irradiation, holes low in mobility are let away to a source electrode via the nitride film to thereby suppress the amount of plus fixed electric charges stored in the LOCOS film. The provision of such a three-layer structure permits improvement in radiation resistance and increase in withstand voltage.Type: ApplicationFiled: June 16, 2009Publication date: December 17, 2009Applicant: FUJI ELECTRIC DEVICE TECHNOLOGY CO., LTD.Inventor: Yasumasa WATANABE
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Publication number: 20090303765Abstract: An error voltage Verr, being a difference between DC output voltage Vout and output reference voltage Vref, and an input voltage Vin are multiplied to produce first threshold voltage signal Vth1 in phase with and similar to input voltage Vin and proportional to Verr. Second threshold voltage signal Vth2 is produced from first threshold voltage signal Vth1. The input current is detected as a current detection signal Vi across a resistor 12, whether it is between the threshold value signals is detected by a current range detecting circuit, and accordingly, the timing of turning on or off switching device is controlled so that at least one of an duration on and an off duration of the switching device is limited to enhance a power factor. Unfixed off duration disperses a noise spectrum to prevent an increase in switching frequency, to reduce noise.Type: ApplicationFiled: June 8, 2009Publication date: December 10, 2009Applicant: Fuji Electric Device Technology Co., LtdInventors: Hideo Shimizu, Isao Amano
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Publication number: 20090302346Abstract: A surface between gate electrodes in an MOS gate structure is patterned so that missing portions are partially provided in surfaces of n+ emitter regions to thereby enlarge surface areas of p+ contact regions surrounded by the surfaces of the n+ emitter regions. In this manner, a highly reliable MOS type semiconductor device is provided which is improved in breakdown tolerance by suppressing an increase in the gain of a parasitic transistor caused by photo pattern defects produced easily in accordance with minute patterning in a process design rule.Type: ApplicationFiled: June 5, 2009Publication date: December 10, 2009Applicant: FUJI ELECTRIC DEVICE TECHNOLOGY CO., LTD.Inventor: Tomoyuki YAMAZAKI
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Publication number: 20090305080Abstract: A perpendicular magnetic recording medium, which includes a nonmagnetic substrate, and a first underlayer in the form of a soft magnetic under-layer (SUL), a second underlayer, an intermediate layer, a magnetic recording layer, a protective layer, and a lubricant layer sequentially laminated on the nonmagnetic substrate. The SUL has a plurality of SUL layers including a type-A SUL layer, a plurality of type-B SUL layers including at least two adjacent type-B SUL layers, and a nonmagnetic metal spacer layer disposed between the two adjacent type-B SUL layers. The type-A SUL layer may include a material selected from Co, Fe and Ni, a material selected from Cr, V and Ti, and a material selected from W, Zr, Ta and Nb. Each of the type-B SUL layers is in antiferromagnetic coupling, and may include a material selected from Co, Fe and Ni, a material selected from Cr, V and Ti, and a material selected from W, Zr, Ta and Nb.Type: ApplicationFiled: June 9, 2009Publication date: December 10, 2009Applicant: Fuji Electric Device Technology Co., Ltd.Inventors: Tuqiang Li, Shunji Takenoiri, Yuko Ueki
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Publication number: 20090296254Abstract: This invention provides a magnetic recording medium evaluation apparatus and evaluation method which yield results having good correlation with error rate measurements even when comparing media with different structures. Signals from a function generator are recorded in a magnetic recording medium. The recording signals are also passed through a first digital filter to obtain ideal restored signals. Reproduced signals from the magnetic recording medium are sampled in synchronization with the output from the function generator, and the discrete signals are passed through a second digital filter to obtain restored signals. The outputs from the first and second digital filters are input to an operational amplifier, and the difference between the restored signals and the ideal restored signals is taken for each sampling of the recording signals. The signal-to-noise ratio of the ideal restored signal to the average of the absolute value of this difference is used to evaluate signal quality.Type: ApplicationFiled: May 28, 2009Publication date: December 3, 2009Applicant: Fuji Electric Device Technology Co., Ltd.Inventor: Takashi Hayashi
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Publication number: 20090294917Abstract: A semiconductor device is manufactured by forming a mask having a first opening and a second opening wider than the first opening on a principal surface of a first conductivity type semiconductor substrate, etching semiconductor portions of the first conductivity type semiconductor substrate exposed in the first and second openings to thereby form a first trench in the first opening and form a second trench deeper than the first trench in the second opening, and filling the first and second trenches with a second conductivity type semiconductor to concurrently form an alignment marker for device production and a junction structure of alternate arrangement of the first conductivity type semiconductor and the second conductivity type semiconductor. In this manner, it is possible to provide a semiconductor device in which a parallel pn structure and an alignment marker can be formed concurrently to improve the efficiency of a manufacturing process.Type: ApplicationFiled: June 2, 2009Publication date: December 3, 2009Applicant: FUJI ELECTRIC DEVICE TECHNOLOGY CO., LTD.Inventor: Ayako YAJIMA
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Publication number: 20090295350Abstract: A reverse current stopping circuit includes a synchronous rectification device, a comparator for detecting a reverse current of an inductor, the synchronous rectification device being turned off when the reverse current is detected by the comparator, a reverse current detector circuit for detecting a switching terminal voltage after the synchronous rectification device is turned off, thereby determining a value of the inductor current to decide whether the inductor current is flowing in a reverse direction or a forward direction, and a memory unit for receiving a predetermined output signal from the reverse current detector circuit in accordance with a result of the reverse current detector circuit, and outputting a control signal for an offset voltage in accordance with the predetermined output signal. The offset voltage is changed in accordance with the control signal so as to adjust the inductor current to zero when the synchronous rectification device is turned off.Type: ApplicationFiled: May 21, 2009Publication date: December 3, 2009Applicant: FUJI ELECTRIC DEVICE TECHNOLOGY CO., LTD.Inventor: Kouhei Yamada
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Patent number: 7626856Abstract: A magnetic recording element is disclosed for which current density required for writing is low and structure of the element is simple. It comprises a ferromagnetic fine wire formed on a Si substrate, current electrodes that contact ends of the ferromagnetic fine wire, and voltage electrodes joined to the ferromagnetic fine wire and current electrodes to measure voltage across part of the ferromagnetic fine wire in cooperation with the current electrodes. A magnetic domain wall is induced in the ferromagnetic fine wire when the element is manufactured. A depression is formed in the surface on top of the ferromagnetic fine wire between the voltage electrodes, and between one of the current electrodes and one of the voltage electrodes. Voltage is measured between the two voltage electrodes when reading current is applied, to determine whether the magnetic domain wall is present between the two voltage electrodes, whereby recorded data can be identified.Type: GrantFiled: March 7, 2007Date of Patent: December 1, 2009Assignee: Fuji Electric Device Technology Co., Ltd.Inventor: Takuya Ono
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Patent number: D606951Type: GrantFiled: November 14, 2008Date of Patent: December 29, 2009Assignee: Fuji Electric Device Technology Co, Ltd.Inventors: Shin Soyano, Akira Nishiura