Abstract: The present invention provides a semiconductor memory device including: a semiconductor substrate of a first conductivity type; and a memory cell including: (i) a columnar semiconductor portion formed on the substrate, (ii) at least two charge-storage layers formed around a periphery of the columnar semiconductor portion and divided in a direction vertical to the semiconductor substrate, and (iii) a control gate that covers at least a portion of charge-storage layers, wherein the memory cell is capable of holding two-bit or more data.

Abstract: A nonvolatile semiconductor storage device including: a plurality of memory cell unit groups each comprising one or more NAND nonvolatile memory cell units each comprising at least one memory cell having a control gate, a first selection transistor having a first selection gate, and a second selection transistor having a second selection gate, the memory cell unit groups each further comprising a control gate line connected to the control gate, a first selection gate line connected to the first selection gate, and a second selection gate line connected to the second selection gate; a common control gate line connected commonly to the control gate lines of different ones of the memory cell unit groups; a first common selection gate line connected commonly to the first selection gate lines of different ones of the memory cell unit groups; and a second common selection gate line connected commonly to the second selection gate lines of different ones of the memory cell unit groups; wherein the memory cells in the

Abstract: The present invention provides a semiconductor memory device comprising: a first conductivity type semiconductor substrate; and a plurality of memory cells constituted of an island-like semiconductor layer which is formed on the semiconductor substrate, and a charge storage layer and a control gate which are formed entirely or partially around a sidewall of the island-like semiconductor layer, wherein the plurality of memory cells are disposed in series, the island-like semiconductor layer which constitutes the memory cells has cross-sectional areas varying in stages in a horizontal direction of the semiconductor substrate, and an insulating film capable of passing charges is provided at least in a part of a plane of the island-like semiconductor layer horizontal to the semiconductor substrate.

Abstract: The present invention provides a semiconductor memory device including: a semiconductor substrate of a first conductivity type; and a memory cell including: (i) a columnar semiconductor portion formed on the substrate, (ii) at least two charge-storage layers formed around a periphery of the columnar semiconductor portion and divided in a direction vertical to the semiconductor substrate, and (iii) a control gate that covers at least a portion of charge-storage layers, wherein the memory cell is capable of holding two-bit or more data.

Abstract: A memory cell unit including: a semiconductor substrate having a source diffusion layer in at least a part of a surface thereof; a column-shaped semiconductor layer provided on the semiconductor substrate, and having a drain diffusion layer provided in an uppermost portion thereof and a first low concentration impurity diffusion layer provided in an entire bottom portion thereof; a memory cell arrangement which includes a plurality of memory cells provided in a peripheral wall of the column-shaped semiconductor layer and connected in series perpendicularly to the substrate, the memory cells each having a charge storage layer and a control gate; a second impurity diffusion layer provided at a lower end of the memory cell arrangement; and a selection transistor having a gate electrode provided around the peripheral wall of the column-shaped semiconductor layer and connecting the second impurity diffusion layer and the first impurity diffusion layer; wherein the first impurity diffusion layer extends into a part

Abstract: A memory cell unit including: a semiconductor substrate having a source diffusion layer provided in a surface thereof; a column-shaped semiconductor layer provided on the source diffusion layer and having a drain diffusion layer provided in an uppermost portion thereof; a memory cell arrangement which includes a plurality of memory cells arranged in series with the intervention of a first impurity diffusion layer; a first selection transistor connected to one end of the memory cell arrangement with the intervention of a second impurity diffusion layer and connected to the drain diffusion layer; and a second selection transistor connected to the other end of the memory cell arrangement with the intervention of a third impurity diffusion layer and connected to the source diffusion layer; wherein a distance between the third impurity diffusion layer and the source diffusion layer is greater than a distance between impurity diffusion layers disposed on opposite sides of each of the memory cells, whereby punch-thr

Abstract: A nonvolatile semiconductor storage device including: a plurality of memory cell unit groups each comprising one or more NAND nonvolatile memory cell units each comprising at least one memory cell having a control gate, a first selection transistor having a first selection gate, and a second selection transistor having a second selection gate, the memory cell unit groups each further comprising a control gate line connected to the control gate, a first selection gate line connected to the first selection gate, and a second selection gate line connected to the second selection gate; a common control gate line connected commonly to the control gate lines of different ones of the memory cell unit groups; a first common selection gate line connected commonly to the first selection gate lines of different ones of the memory cell unit groups; and a second common selection gate line connected commonly to the second selection gate lines of different ones of the memory cell unit groups; wherein the memory cells in the

Abstract: A semiconductor device comprising a memory cell which includes: a pillar-shaped semiconductor layer of a first conductive type formed on a semiconductor substrate; source and drain diffusion layers of a second conductive type formed in upper and lower portions of the pillar-shaped semiconductor layer; a semiconductor layer of the second conductive type or a cavity formed inside the pillar-shaped semiconductor layer; and a gate electrode formed on a side face of the pillar-shaped semiconductor layer via a gate insulating film, or a control gate electrode formed on the side face of the pillar-shaped semiconductor layer via a charge accumulation layer.

Abstract: An ion implantation method for implanting ions into a side wall of a protruded semiconductor layer from a semiconductor substrate, the method includes applying an electric field to accelerate the ions in one direction and applying a magnetic field parallel to a plane extending at a predetermined angle with respect to the one direction, thereby controlling a direction of the ion implantation to the side wall.

Abstract: A method for driving a nonvolatile memory device including a semiconductor substrate, an island semiconductor layer on the substrate, a memory cell having a control gate and a charge storage layer surrounding a peripheral surface of the island semiconductor layer, a first selection transistor provided between the memory cell and the substrate and having a first selection gate, a source diffusion layer between the substrate and the island semiconductor layer, a drain diffusion layer provided in an opposing end of the island semiconductor layer from the source diffusion layer, and a second selection transistor provided between the memory cell and the drain diffusion layer and having a second selection gate, the method comprising the steps of: applying a negative first voltage to the drain and the first selection gate, applying a positive second voltage to the second selection gate, and applying 0V or a positive third voltage to the source; and applying a positive fourth voltage higher than the second voltage to

Abstract: A semiconductor device including: a silicon pillar having a high-resistivity region and first and second highly doped regions sandwiching the high-resistivity region therebetween, the high-resistivity region having an impurity concentration of 1017 cm−3 or less; an insulator surrounding the high-resistivity region; and a conductor surrounding the insulator, wherein the conductor is made of a material which permits a voltage applied to the conductor to control an electric current flowing between the first and second highly doped regions and which has a work function bringing the high-resistivity region to a perfect depletion condition during the flow of the electric current between the first and second highly doped regions.

Abstract: The present invention provides a semiconductor memory device comprising one or more protruding semiconductor layers formed on a semiconductor substrate of a first conductivity type and a plurality of memory cells on surfaces of the protruding semiconductor layers, wherein