Abstract: The invention provides a clock distribution circuit which can be applied readily also to a chip (semiconductor integrated circuit) of the building block type and can realize reduction in skew. The clock distribution circuit includes a first buffer disposed at a central location of the chip for receiving an output of an input driver, four second buffers individually disposed at central locations of four sides of the chip for receiving an output of the first buffer, a plurality of third buffers for receiving outputs of the second buffers, and a last stage connection wiring line system for connecting all of outputs of the third buffers commonly to extract a clock signal to be supplied to clock terminals. The third buffers are disposed on linear lines parallel to the two upper and lower sides of the chip, and the outputs of the third buffers are connected to each other by linear wiring lines.

Abstract: A display system includes a plurality of display areas on which images are displayed, and a processing unit for controlling display formation of images on the plurality of display areas so that the images are displayed with predetermined orientations different from each other. Another type of display system includes a display panel on which an image is displayed, and a processing unit for controlling display formation of an image on the display panel so that the image is displayed rotated by an angle.