Abstract: A wireless communication apparatus includes: an optical sensor; and a wireless communication circuit configured to execute a transmission process that transmits a first signal based on data stored in a storage element and a reception process that receives a second signal in response to the transmission of the first signal, wherein the wireless communication circuit is further configured to write data to the storage element in accordance with the second signal received in the reception process when an output level of the optical sensor is in a first state in which the output level of the optical sensor is equal to or higher than a predetermined threshold.

Abstract: A high frequency module includes: a semiconductor chip provided over a first surface side of a resin layer; a first waveguide provided over the first surface side of the resin layer and sealed together with the semiconductor chip by a resin; a wire provided over a second surface side of the resin layer and electrically coupled to the semiconductor chip and extending to a position of the first waveguide; a second waveguide bonded to the first waveguide; and a metal plate provided over the first surface side of the resin layer at a position opposite to the first waveguide and electrically coupled to the wire, wherein a part of the wire extending to the position of the first waveguide serves as an antenna coupler.

Abstract: A rate adjustment apparatus includes a calculating section to calculate a number of outputs where bits of input data are sequentially output when a number of times of puncturing of the input data to be punctured is smaller than a number of remaining bits after puncturing, and a processing section to sequentially output bits of the input data and puncture the bits of the input data based on the number of outputs calculated by the calculating section.

Abstract: An optical module which can achieve miniaturization, high performance and cost reduction is, provided. The optical module includes a photoelectric component, a high-speed signal processing part which processes a high-speed signal photoelectrically converted by the photoelectric component, and a low-speed signal processing part which processes a low-speed signal. The high-speed signal processing part and the low-speed signal processing part are overlapped with each other in a vertical direction and electrically connected to each other.

Abstract: The invention provides a clock distribution circuit which can be applied readily also to a chip (semiconductor integrated circuit) of the building block type and can realize reduction in skew. The clock distribution circuit includes a first buffer disposed at a central location of the chip for receiving an output of an input driver, four second buffers individually disposed at central locations of four sides of the chip for receiving an output of the first buffer, a plurality of third buffers for receiving outputs of the second buffers, and a last stage connection wiring line system for connecting all of outputs of the third buffers commonly to extract a clock signal to be supplied to clock terminals. The third buffers are disposed on linear lines parallel to the two upper and lower sides of the chip, and the outputs of the third buffers are connected to each other by linear wiring lines.

Abstract: A display system includes a plurality of display areas on which images are displayed, and a processing unit for controlling display formation of images on the plurality of display areas so that the images are displayed with predetermined orientations different from each other. Another type of display system includes a display panel on which an image is displayed, and a processing unit for controlling display formation of an image on the display panel so that the image is displayed rotated by an angle.