Patents Assigned to FUJITSU ADVANCED ENGINEERING
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Patent number: 10382250Abstract: A disclosed system includes plural switches, a node, and a management apparatus. The node includes: a transmitter that transmits an assignment request whose destination is the management apparatus. The management apparatus includes: a determination unit that determines whether an identifier can be assigned to the node, based on the assignment request; and a transmitter that transmits a response including an identifier assigned to the node. And a first switch that is a switch of the plural switches and relays the assignment request and the response includes: a making unit that makes settings for relaying a packet whose destination is the node; and a transmitter that transmits, to other switches belonging to a domain to which the first switch belongs, a setting request including the information on the logical link that received the assignment request and the identifier included in the response.Type: GrantFiled: December 18, 2015Date of Patent: August 13, 2019Assignees: FUJITSU LIMITED, FUJITSU ADVANCED ENGINEERING LIMITEDInventors: Osamu Shiraki, Hiroyuki Esashi
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Patent number: 9972207Abstract: An information collection system includes a first communication device provided at a first vehicle including a processor configured to execute a process. The process includes receiving operations by a first input section, and wirelessly transmitting, by a first transmission section, specific information according to the operation received by the first input section. The information collection system further includes a second communication device provided at a second vehicle including a processor configured to execute a process. The process includes receiving, by a first reception section, the specific information transmitted by the first transmission section, and wirelessly transmitting, to a device that is different from the first communication device by a second transmission section, position information enabling identification of a position at which the specific information was received by the first reception section.Type: GrantFiled: March 25, 2016Date of Patent: May 15, 2018Assignee: FUJITSU ADVANCED ENGINEERING LIMITEDInventors: Yoshitoshi Kurose, Kazuki Ota, Ryutaro Motora, Shota Irie, Tomomi Nishida
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Patent number: 9419434Abstract: A power switching apparatus includes: a first input terminal to which first power is supplied; a second input terminal to which second power is supplied, the second power having a voltage that is lower than a voltage that the first power has; a first output terminal to supply to an outside the first power supplied to the first input terminal; and a second output terminal to supply to the outside the second power supplied to the second input terminal. First switching means manages the supplying of the second power from the first input terminal to the second output terminal. Second switching means manages the supplying of the second power from the second input terminal to the second output terminal. A processor manages the supplies of the first power and the second power using the first and second switching means.Type: GrantFiled: April 16, 2014Date of Patent: August 16, 2016Assignees: FUJITSU LIMITED, FUJITSU ADVANCED ENGINEERING LIMITEDInventors: Susumu Eguchi, Takahiro Kamei
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Publication number: 20160191299Abstract: A disclosed system includes plural switches, a node, and a management apparatus. The node includes: a transmitter that transmits an assignment request whose destination is the management apparatus. The management apparatus includes: a determination unit that determines whether an identifier can be assigned to the node, based on the assignment request; and a transmitter that transmits a response including an identifier assigned to the node. And a first switch that is a switch of the plural switches and relays the assignment request and the response includes: a making unit that makes settings for relaying a packet whose destination is the node; and a transmitter that transmits, to other switches belonging to a domain to which the first switch belongs, a setting request including the information on the logical link that received the assignment request and the identifier included in the response.Type: ApplicationFiled: December 18, 2015Publication date: June 30, 2016Applicants: FUJITSU LIMITED, FUJITSU ADVANCED ENGINEERING LIMITEDInventors: Osamu SHIRAKI, Hiroyuki ESASHI
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Patent number: 9329959Abstract: A basic input/output system (BIOS) storage unit stores therein a BIOS. An operating system (OS) storage unit stores therein a plurality of OSs. A boot control unit sequentially starts the OSs stored in the OS storage unit. When each of the OSs booted by the boot control unit starts up, a boot information acquisition unit acquires boot information transferred between the OS and the BIOS. A regression analysis processing unit compares the boot information acquired by the boot information acquisition unit with expected values which are predetermined values for the boot information to determine whether the boot information coincides with the expected values.Type: GrantFiled: August 20, 2013Date of Patent: May 3, 2016Assignees: FUJITSU LIMITED, FUJITSU ADVANCED ENGINEERING LIMITEDInventors: Manabu Kanaya, Yasushi Sekiguchi, Takashi Ohhashi
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Publication number: 20140225438Abstract: A power switching apparatus includes: a first input terminal to which first power is supplied; a second input terminal to which second power is supplied, the second power having a voltage that is lower than a voltage that the first power has; a first output terminal to supply to an outside the first power supplied to the first input terminal; and a second output terminal to supply to the outside the second power supplied to the second input terminal. First switching means manages the supplying of the second power from the first input terminal to the second output terminal. Second switching means manages the supplying of the second power from the second input terminal to the second output terminal. A processor manages the supplies of the first power and the second power using the first and second switching means.Type: ApplicationFiled: April 16, 2014Publication date: August 14, 2014Applicants: FUJITSU LIMITED, FUJITSU ADVANCED ENGINEERING LIMITEDInventors: Susumu Eguchi, Takahiro Kamei
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Publication number: 20130339718Abstract: A basic input/output system (BIOS) storage unit stores therein a BIOS. An operating system (OS) storage unit stores therein a plurality of OSs. A boot control unit sequentially starts the OSs stored in the OS storage unit. When each of the OSs booted by the boot control unit starts up, a boot information acquisition unit acquires boot information transferred between the OS and the BIOS. A regression analysis processing unit compares the boot information acquired by the boot information acquisition unit with expected values which are predetermined values for the boot information to determine whether the boot information coincides with the expected values.Type: ApplicationFiled: August 20, 2013Publication date: December 19, 2013Applicants: FUJITSU ADVANCED ENGINEERING LIMITED, FUJITSU LIMITEDInventors: Manabu KANAYA, Yasushi Sekiguchi, Takashi Ohhashi
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Publication number: 20110314291Abstract: When input data (f0) is read into a digital signature generating apparatus, a hash value (h0) is calculated. The hash value (h0) is stored to a storage area (M1), which has the highest priority rank among 5 storage areas. Subsequently, when input data (f1) is read in, a hash value (h1) is calculated. Since the storage area (M1) is already occupied by the hash value (h0), the hash value (h0) is read out from storage area (M1), emptying the storage area (M1). The read hash value (h0) and the hash value (h1) are concatenated, forming a concatenated hash value (h0|h1) and a hash value (h0,1) is calculated. The hash value (h0,1) is stored to a storage area (M2), which has the highest priority rank after the storage area (M1). When input data (f2) is read in, a hash value (h2) is calculated and stored to the storage area (M1).Type: ApplicationFiled: August 24, 2011Publication date: December 22, 2011Applicants: FUJITSU ADVANCED ENGINEERING LIMITED, FUJITSU LIMITEDInventors: Masahiko Takenaka, Takashi Yoshioka, Fumitsugu Matsuo, Fumiaki Chiba
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Publication number: 20110302419Abstract: An image managing method includes dividing the original moving image into a header and a body and generating the group hash value of the header portion, generating the hash value of each item of still image data, connecting the group hash value of the header portion and the hash value of each item of still image data to generate connected hash values, generating a group of the connected hash values as a hash value list, generating the hash value of a Huffman table on the basis of cutting out one still image, and signing to generate signature information of the original moving image, using the group hash value of the header portion, the hash value of the Huffman table, and the hash list as verification data of the original moving image, by adding a digital signature of a video recording terminal to it.Type: ApplicationFiled: August 22, 2011Publication date: December 8, 2011Applicants: FUJITSU ADVANCED ENGINEERING, FUJITSU LIMITEDInventors: Takashi YOSHIOKA, Fumitsugu Matsuo, Kiyohide Yamashita, Fumiaki Chiba