Patents Assigned to Fujitsu Amd Semiconductor Limited
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Patent number: 7679194Abstract: Disclosed is a method of fabricating a semiconductor memory device including the step of irradiating ultraviolet rays on a metal interconnection at a bonding pad part, so that the metal interconnection can be prevented from being corroded because of a corrodent element in the process of erasing charges stored in a charge storage part. An oxide coating film is formed on the surface of the metal interconnection at the bonding pad part, and ultraviolet rays are irradiated onto the oxide coating film for erasing of charges from the floating gate.Type: GrantFiled: April 10, 2007Date of Patent: March 16, 2010Assignee: Fujitsu AMD Semiconductor LimitedInventors: Tatsuya Hashimoto, Toshiyuki Maenosono, Taji Togawa, Takayuki Enda, Hideo Takagi
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Publication number: 20070187833Abstract: Disclosed is a method of fabricating a semiconductor memory device including the step of irradiating ultraviolet rays on a metal interconnection at a bonding pad part, so that the metal interconnection can be prevented from being corroded because of a corrodent element in the process of erasing charges stored in a charge storage part. An oxide coating film is formed on the surface of the metal interconnection at the bonding pad part, and ultraviolet rays are irradiated onto the oxide coating film for erasing of charges from the floating gate.Type: ApplicationFiled: April 10, 2007Publication date: August 16, 2007Applicant: Fujitsu Amd Semiconductor LimitedInventors: Tatsuya Hashimoto, Toshiyuki Maenosono, Taji Togawa, Takayuki Enda, Hideo Takagi
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Publication number: 20060228899Abstract: After a lower silicon oxide film is formed on a silicon region, a silicon film is formed on the lower silicon oxide film by, for example, a thermal CVD method. Subsequently, the silicon film is completely nitrided by a plasma nitriding method to be replaced by a silicon nitride film. Subsequently, a surface layer of the silicon nitride film is oxidized by a plasma oxidizing method to be replaced by an upper silicon oxide film. An ONO film as a multilayered insulating film composed of the lower silicon oxide film, the silicon nitride film, and the upper silicon oxide film is formed.Type: ApplicationFiled: May 26, 2006Publication date: October 12, 2006Applicant: FUJITSU AMD SEMICONDUCTOR LIMITEDInventors: Hiroyuki Nansei, Manabu Nakamura, Kentaro Sera, Masahiko Higashi, Yukihiro Utsuno, Hideo Takagi, Tatsuya Kajita
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Patent number: 7098147Abstract: After a lower silicon oxide film is formed on a silicon region, a silicon film is formed on the lower silicon oxide film by, for example, a thermal CVD method. Subsequently, the silicon film is completely nitrided by a plasma nitriding method to be replaced by a silicon nitride film. Subsequently, a surface layer of the silicon nitride film is oxidized by a plasma oxidizing method to be replaced by an upper silicon oxide film. An ONO film as a multilayered insulating film composed of the lower silicon oxide film, the silicon nitride film, and the upper silicon oxide film is formed.Type: GrantFiled: August 20, 2003Date of Patent: August 29, 2006Assignee: Fujitsu Amd Semiconductor LimitedInventors: Hiroyuki Nansei, Manabu Nakamura, Kentaro Sera, Masahiko Higashi, Yukihiro Utsuno, Hideo Takagi, Tatsuya Kajita
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Publication number: 20050212035Abstract: Tunnel insulating films (3) are formed in element regions demarcated by element isolation insulating films (2). Thereafter, for each memory cell, a floating gate (4) is formed, and an ONO film (5) and a control gate (6) are further formed. Next, a plasma insulating film (7) is formed on surfaces of stacked gates. The plasma insulating film is immune to plane orientation of a base film. Therefore, the entire plasma insulating film (7) has a substantially uniform thickness, and consequently, even if the maximum thickness thereof is not as large as that of a thermal oxide film, hydrogen entrance is prevented when the interlayer insulating film is thereafter formed, and electron leakage is also prevented. The reduction in thickness of this insulating film makes it possible to reduce birds' beaks, and efficiency in erase/write of data can be enhanced.Type: ApplicationFiled: February 25, 2005Publication date: September 29, 2005Applicant: FUJITSU AMD SEMICONDUCTOR LIMITEDInventors: Yukihiro Utsuno, Manabu Nakamura, Kentaro Sera, Masahiko Higashi, Hiroyuki Nansei, Hideo Takagi, Tatsuya Kajita
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Publication number: 20050212074Abstract: A trench (4) is formed in a semiconductor substrate (1), and then a plasma oxynitride film (5) is formed on a side wall surface and a bottom surface of the trench (4) at a temperature of approximately 300° C. to 650° C. At such a temperature, no outward diffusion of impurities from the semiconductor substrate (1) occurs. Therefore, any problems such as formation of a parasitic transistor hardly occur even when ions of impurities are not implanted thereafter. After the plasma oxynitride film (5) is formed, it is thermally oxidized, and a portion where the outermost surface of the semiconductor substrate (1) meets the wall surface of the trench (4) is turned into a curved surface. As a result, the outermost surface of the semiconductor substrate (1) and the wall surface of the trench (4) meet each other while forming a curved surface, and hence a parasitic transistor is hardly formed at this portion. Consequently, formation of a hump is prevented, thereby achieving favorable characteristics.Type: ApplicationFiled: February 25, 2005Publication date: September 29, 2005Applicant: FUJITSU AMD SEMICONDUCTOR LIMITEDInventors: Kentaro Sera, Hiroyuki Nansei, Manabu Nakamura, Masahiko Higashi, Yukihiro Utsuno, Hideo Takagi, Tatsuya Kajita
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Publication number: 20050006672Abstract: Disclosed is a method of fabricating a semiconductor memory device including the step of irradiating ultraviolet rays on a metal interconnection at a bonding pad part, so that the metal interconnection can be prevented from being corroded because of a corrodent element in the process of erasing charges stored in a charge storage part. An oxide coating film is formed on the surface of the metal interconnection at the bonding pad part, and ultraviolet rays are irradiated onto the oxide coating film for erasing of charges from the floating gate.Type: ApplicationFiled: August 12, 2004Publication date: January 13, 2005Applicant: Fujitsu AMD Semiconductor LimitedInventors: Tatsuya Hashimoto, Toshiyuki Maenosono, Taiji Togawa, Takayuki Enda, Hideo Takagi
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Patent number: 6794248Abstract: Disclosed is a method of fabricating a semiconductor memory device including the step of irradiating ultraviolet rays on a metal interconnection at a bonding pad part, so that the metal interconnection can be prevented from being corroded because of a corrodent element in the process of erasing charges stored in a charge storage part. An oxide coating film is formed on the surface of the metal interconnection at the bonding pad part, and ultraviolet rays are irradiated onto the oxide coating film for erasing of charges from the floating gate.Type: GrantFiled: October 25, 2002Date of Patent: September 21, 2004Assignee: Fujitsu Amd Semiconductor LimitedInventors: Tatsuya Hashimoto, Toshiyuki Maenosono, Taiji Togawa, Takayuki Enda, Hideo Takagi
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Publication number: 20040043638Abstract: After a lower silicon oxide film is formed on a silicon region, a silicon film is formed on the lower silicon oxide film by, for example, a thermal CVD method. Subsequently, the silicon film is completely nitrided by a plasma nitriding method to be replaced by a silicon nitride film. Subsequently, a surface layer of the silicon nitride film is oxidized by a plasma oxidizing method to be replaced by an upper silicon oxide film. An ONO film as a multilayered insulating film composed of the lower silicon oxide film, the silicon nitride film, and the upper silicon oxide film is formed.Type: ApplicationFiled: August 20, 2003Publication date: March 4, 2004Applicant: FUJITSU AMD SEMICONDUCTOR LIMITEDInventors: Hiroyuki Nansei, Manabu Nakamura, Kentaro Sera, Masahiko Higashi, Yukihiro Utsuno, Hideo Takagi, Tatsuya Kajita
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Patent number: 6670616Abstract: Irradiation lamps of an ultraviolet-light irradiation apparatus are uniformly cooled to achieve an appropriate temperature of the walls of the lamps and the ultraviolet light emitted from the lamps is efficiently reflected toward an object to be irradiated so that the ultraviolet light is efficiently irradiated onto the object to be irradiated. A plurality of low-pressure mercury lamps are arranged in parallel. A reflective mirror is arranged above the low-pressure mercury lamps so as to reflect the ultraviolet light emitted by the low-pressure mercury lamps. An exhaust passage defined by the reflective mirror suctions air around the low-pressure mercury lamps and exhausts the suctioned air to outside. The reflective mirror has a plurality of openings arranged along a longitudinal direction of the low-pressure mercury lamps, and a part of the openings has a size different from a size of other parts of the openings.Type: GrantFiled: March 22, 2002Date of Patent: December 30, 2003Assignee: Fujitsu AMD Semiconductor LimitedInventor: Kenji Kikuchi
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Publication number: 20030162354Abstract: Disclosed is a method of fabricating a semiconductor memory device including the step of irradiating ultraviolet rays on a metal interconnection at a bonding pad part, so that the metal interconnection can be prevented from being corroded because of a corrodent element in the process of erasing charges stored in a charge storage part. An oxide coating film is formed on the surface of the metal interconnection at the bonding pad part, and ultraviolet rays are irradiated onto the oxide coating film for erasing of charges from the floating gate.Type: ApplicationFiled: October 25, 2002Publication date: August 28, 2003Applicant: FUJITSU AMD SEMICONDUCTOR LIMITEDInventors: Tatsuya Hashimoto, Toshiyuki Maenosono, Taiji Togawa, Takayuki Enda, Hideo Takagi
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Patent number: 6232663Abstract: A semiconductor device and a method of fabricating thereof, including an insulator layer having alternately layered insulator films and boundary layers, wherein the boundary layers are more dense than the insulator films to prevent expansion and elongation of string-like defects across the boundary layers. The method includes mixing a nitrogen containing gas and a silane group gas to form an insulator film; temporarily stopping a flow of the silane group gas for approximately one to fifteen seconds to form a boundary layer over the insulator film; restarting the flow of the silane group gas; and repeating the steps of temporarily stopping and restarting for a predetermined number of times to form the plurality of alternately layered insulator films and boundary layers. The plurality of alternately layered insulator films and boundary layers is also etched at an etching rate for the insulator films greater than an etching rate for the boundary layers to form a step-shaped sloped opening.Type: GrantFiled: August 1, 1997Date of Patent: May 15, 2001Assignees: Fujitsu Limited, Advanced Micro Devices, Inc., Fujitsu AMD, Semiconductor LimitedInventors: Toshio Taniguchi, Kenji Nukui, Ibrahim Burki, Richard Huang, Simon Chan, Kazunori Imaoka, Kazutoshi Mochizuki
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Patent number: 6187640Abstract: In a method of manufacturing a semiconductor device, there are comprised the steps of forming an oxidation preventing layer on a surface of a semiconductor substrate, forming first window in the oxidation preventing layer, placing the semiconductor substrate in a first atmosphere in which an oxygen gas and a first amount of a chlorine gas are supplied through and then heating the semiconductor substrate at a first temperature such that a first selective oxide film is to grown by thermally oxidizing the surface of the semiconductor substrate exposed from the first window, forming a second window by patterning the oxidation preventing layer, and placing the semiconductor substrate in a second atmosphere in which the oxygen gas and a second amount, which is larger than the first amount, of the chlorine gas are supplied through and then heating the semiconductor substrate at a second temperature such that a second selective oxide film is formed and that a thickness of the first selective oxide film formed below tType: GrantFiled: November 17, 1998Date of Patent: February 13, 2001Assignees: Fujitsu Limited, Advanced Micro Devices, Inc., Fujitsu Amd Semiconductor LimitedInventors: Hiroyuki Shimada, Masaaki Higashitani, Hideo Kurihara, Hideki Komori, Satoshi Takahashi
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Patent number: 6177312Abstract: This invention relates to a method for removing contaminate nitrogen from the peripheral gate region of a non-volatile memory device during production of said device, wherein at least some of the contaminate nitrogen has formed a bond with the surface of the silicon substrate in contact with the gate oxide layer in said gate region, said method comprising: contacting said gate oxide layer and contaminate nitrogen with a gas comprising ozone at a temperature of about 850° C. to about 950° C. for an effective period of time to break said bond; and removing said gate oxide layer and contaminate nitrogen from said surface of said silicon substrate.Type: GrantFiled: March 26, 1998Date of Patent: January 23, 2001Assignees: Advanced Micro Devices, Inc., Fujitsu, Ltd., Fujitsu AMD Semiconductor Limited (FASL)Inventors: Yuesong He, John Jianshi Wang, Toru Ishigaki, Kent Kuohua Chang, Effiong Ibok
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Patent number: 6057193Abstract: A method (200) of forming a NAND type flash memory device includes the steps of forming an oxide layer (202) over a substrate (102) and forming a first conductive layer (106) over the oxide layer. The first conductive layer (106) is etched to form a gate structure (107) in a select gate transistor region (105) and a floating gate structure (106a, 106b) in a memory cell region (111). A first insulating layer (110) is then formed over the memory cell region (111) and a second conductive layer (112, 118) is formed over the first insulating layer (110). A word line (122) is patterned in the memory cell region (111) to form a control gate region and source and drain regions (130, 132) are formed in the substrate (102) in a region adjacent the word line (122) and in a region adjacent the gate structure (107).Type: GrantFiled: April 16, 1998Date of Patent: May 2, 2000Assignees: Advanced Micro Devices, Inc., Fujitsu Limited, Fujitsu AMD Semiconductor LimitedInventors: John Jianshi Wang, Hao Fang, Masaaki Higashitani
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Patent number: 5907781Abstract: A method of forming a contact in a flash memory device utilizes a local interconnect process technique. The local interconnect process technique allows the contact to butt against or overlap a stacked gate associated with the memory cell. The contact can include tungsten. The stacked gate is covered by a barrier layer which also covers the insulative spacers.Type: GrantFiled: March 27, 1998Date of Patent: May 25, 1999Assignees: Advanced Micro Devices, Inc., Fujitsu Limited, Fujitsu AMD Semiconductor LimitedInventors: Hung-Sheng Chen, Unsoon Kim, Yu Sun, Chi Chang, Mark Ramsbey, Mark Randolph, Tatsuya Kajita, Angela Hui, Fei Wang, Mark Chang