Abstract: Ultrasonic generating unit of a cleaning tank in a cleaning apparatus applies ultrasonic waves to cleaning fluid supplied into the cleaning tank from a supply port and fluid jetting unit having openings at locations corresponding to areas to be cleaned of an article to be cleaned jets the ultrasonic-applied cleaning fluid from the openings to the areas to be cleaned of the article to be cleaned.

Abstract: The cleaning apparatus for cleaning a cleaning target set in a cleaning tank filled with a washing fluid includes a flow-control unit for generating a predetermined flow of the washing fluid in the cleaning tank; and an ejection unit for ejecting the washing fluid disposed on a flow path of the predetermined flow of the washing fluid. The cleaning apparatus ejects the washing fluid to outside the cleaning tank by using the ejection unit in removing contaminants on a surface of the cleaning target by washing the cleaning target with the washing fluid. Also, a cleaning tank having substantially the same structure as that of the cleaning apparatus is provided. Moreover, a cleaning method implemented using the cleaning apparatus as described above or the like is provided.

Abstract: A disconnection-inspecting method for inspecting an electrical disconnection between circuits formed on both surfaces of a board is provided. The method includes the steps of: placing the board on an insulating sheet laid on a reference conductor; measuring a first capacitance between the reference conductor and one of the circuits formed on a surface of both surfaces opposite to the other surface facing the insulating sheet; measuring a second capacitance between the reference conductor and the one of the circuits by changing a first physical quantity of the insulating sheet; calculating a second physical quantity of each of the circuits based on the first capacitance and the second capacitance measured in the steps of measuring; and judging the presence of the electrical disconnection based on the second physical quantity calculated in the step of calculating.

Abstract: A method of producing semiconductor devices which have an excellent separability from a metal mold after resin encapsulation and thus eliminates the need to clean the metal mold. A metal mold for producing such semiconductor devices is also provided. According to the method of the present invention, the metal mold is first opened, and two separation sheets are disposed on dividing surfaces including cavity forming surfaces of a first metal mold and a second metal mold. A substrate is then placed on one of the separation sheets, with its semiconductor chip formed surface facing the second metal mold. An encapsulation resin is provided on the substrate placed on one of the separation sheets. The metal mold in a heated state is closed and pressed to form a resin layer for encapsulating electrodes formed on the substrate. The metal mold is again opened, and the resin-encapsulated substrate is taken out of the metal mold.

Abstract: A semiconductor device includes a semiconductor element, a semiconductor device base member having an element mounting portion on which the semiconductor element is mounted, external connection terminals provided on the semiconductor device base member and electrically connected to the semiconductor element, and a resin sealing the semiconductor element. The semiconductor device base member includes a base part and lead parts supported by the base part. The lead parts are electrically connected to the external connection terminals. The semiconductor device base member has bent portions in which the lead parts are located on outer sides of the semiconductor device base member. The bent portions are located in edge portions of the semiconductor device base member.

Abstract: The present invention is a simulation apparatus which can shorten the transmission and reception time of events, and unify simulation models to make it possible to use the same language expression as that for an ordinary model to express a real chip. The simulation apparatus comprises a real chip simulation section for carrying out simulation for a portion having an unknown internal logic by using a real chip, a logic simulation hardware section for carrying out simulation for a portion whose internal logic is described, and a high speed dedicated network for transferring event data between the real chip simulation section and the logic simulation hardware section. The simulation apparatus can be applied to hardware accelerators used in logic timing simulation in the field of CAE.

Abstract: A semiconductor device including a plurality of leads respectively made up of an inner lead and an outer lead, a semiconductor chip electrically connected to the inner leads, and a package encapsulating at least the inner leads of the leads and the semiconductor chip so that the outer leads extend outwardly of the package. The package has an upper part and a lower part which have mutually different sizes such that a stepped part is formed between the upper and lower parts by the different sizes, and each of the outer leads have a wide part which is wider than other parts of the outer lead extending outwardly of the package only within the stepped part of the package.

Abstract: A semiconductor device includes a semiconductor element, a semiconductor device base member having an element mounting portion on which the semiconductor element is mounted, external connection terminals provided on the semiconductor device base member and electrically connected to the semiconductor element, and a resin sealing the semiconductor element. The semiconductor device base member includes a base part and lead parts supported by the base part. The lead parts are electrically connected to the external connection terminals. The semiconductor device base member has bent portions in which the lead parts are located on outer sides of the semiconductor device base member. The bent portions are located in edge portions of the semiconductor device base member.

Abstract: For a print-circuit board 10 of a good product, probes 31 and 32 are made to be electrically continuous with a ground plate 13 and a wiring pattern i respectively to measure a capacitance Cgi, which is then stored in a storage device 44. A capacitance Ci of a print-circuit board 10, the object of testing, is measured in a similar manner and a ratio .mu.=(average value Ca of a several measured capacitance value of the object of testing/(average value Cga of the corresponding measured capacitance values of the good product) is calculated. If Ci<Cgj(1-.DELTA.e0) or Ci>Cgj(1+.DELTA.e0), the measured capacitance values Ci and Cgjare excluded from the objects of calculation of the average values. If Cj<.mu..Cgj(1-.DELTA.e) or Cj>.mu..Cgj(1+.DELTA.e), a wiring j is judged to be defective and the resistance measuring method is employed to judge the details of the defect. The tolerance rate .DELTA.e0 and .DELTA.e are 0.15 and 0.02 respectively.

Abstract: A process for manufacturing semiconductor device including a plurality of leads respectively made up of an inner lead and an outer lead, a semiconductor chip electrically connected to the inner leads, and a package encapsulating at least the inner leads of the leads and the semiconductor chip so that the outer leads extend outwardly of the package. The package has an upper part and a lower part which have mutually different sizes such that a stepped part is formed between the upper and lower parts by the different sizes, and each of the outer leads have a wide part which is wider than other parts of the outer lead extending outwardly of the package only within the stepped part of the package.

Abstract: A semiconductor device comprises a plurality of leads respectively made up of an inner lead and an outer lead, a semiconductor chip electrically connected to the inner leads of the leads, and a package encapsulating at least the inner leads of the leads and the semiconductor chip so that the outer leads extend outwardly of the package. The package has an upper part and a lower part which have mutually different sizes such that a stepped part is formed between the upper and lower parts by the different sizes, and each of the outer leads have a wide part which is wider than other parts of the outer lead extending outwardly of the package only within the stepped part of the package.

Abstract: A semiconductor device including a plurality of leads respectively made up of an inner lead and an outer lead, a semiconductor chip electrically connected to the inner leads, and a package encapsulating at least the inner leads of the leads and the semiconductor chip so that the outer leads extend outwardly of the package. The package has an upper part and a lower part which have mutually different sizes such that a stepped part is formed between the upper and lower parts by the different sizes, and each of the outer leads have a wide part which is wider than other parts of the outer lead extending outwardly of the package only within the stepped part of the package.

Abstract: In a logic simulation apparatus formed of dedicated hardware for simulating a logic operation of at least one logic circuit, and connected to at least one host computer, the apparatus includes: a plurality of clusters, each cluster including at least a communication network and a plurality of processor elements connected each other through the communication network; and an upper communication network for connecting among clusters. The host computer is connected to at least one cluster, and the connection configuration among the plurality of clusters is changeable in accordance with the size of the logic operation to be simulated under instructions of configuration change generated by the host computer. The apparatus further includes an error analysis system for the simulation process.

Abstract: A semiconductor device comprises a plurality of leads respectively made up of an inner lead and an outer lead, a semiconductor chip electrically connected to the inner leads of the leads, and a package encapsulating at least the inner leads of the leads and the semiconductor chip so that the outer leads extend outwardly of the package. The package has an upper part and a lower part which have mutually different sizes such that a stepped part is formed between the upper and lower parts by the different sizes, and each of the outer leads have a wide part which is wider than other parts of the outer lead extending outwardly of the package only within the stepped part of the package.

Abstract: Fish sex discrimination equipment and method comprising an automatic supplying unit, a light projection and reception detection unit, a discrimination control unit, a discharge unit, and a first conveyor and a second conveyor, and also comprising the steps of automatically supplying fish to be discriminated, transmitting light to a genital gland area of the fish, scanning the light, discriminating the sex of the fish based on the quantity of light tramsmitted, for example, a mean value or integrated value, and discharging the fish through the first or second conveyor which corresponds to the sex of the fish.