Patents Assigned to Fujitsu Client Computing Limited
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Publication number: 20200265000Abstract: An information processing system according to one embodiment includes platforms and a relay device including an expansion bus that connects between the platforms. Each platform includes a memory that stores transmit data to another platform through transactions occurring in the platform concerned; a controller that reads first transmit data from the memory, and transmits the first transmit data to the another platform through a first transaction among the transactions via the expansion bus; determines whether a second transaction higher in priority than the first transaction is occurring in the platform after completion of transmission of each packet of the first transmit data; and in response to the second transaction, reads second transmit data from the memory, transmits the second transmit data to the another platform through the second transaction via the expansion bus, and interrupts transmission of the first transmit data until completion of transmission of the second transmit data.Type: ApplicationFiled: February 18, 2020Publication date: August 20, 2020Applicant: FUJITSU CLIENT COMPUTING LIMITEDInventor: Masaharu Nagata
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Publication number: 20200264259Abstract: A position determination apparatus includes a memory and a hardware processor coupled to the memory. The hardware processor: determines position information on one or more wireless communication devices being located within a target region; judges position movement of the one or more wireless communication devices based on the position information; and transmits, to the wireless communication device whose position movement has been judged to be absent, a decrease instruction signal that causes the wireless communication device to decrease a communication frequency of the wireless communication device.Type: ApplicationFiled: January 24, 2020Publication date: August 20, 2020Applicant: FUJITSU CLIENT COMPUTING LIMITEDInventor: Keita Satou
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Publication number: 20200257993Abstract: An information processing system includes: a failure detector, a first failure handling unit and a second failure handling unit. The failure detector detects any of inference processing apparatuses in which a failure has occurred. The first failure handling unit causes another inference processing apparatus other than the inference processing apparatus in which the failure has occurred to execute an inference process of the inference processing apparatus in which the failure has occurred. The second failure handling unit inputs a result of an inference process at a preceding stage of the inference processing apparatus in which the failure has occurred to the another inference processing apparatus and outputs an inference result that the another inference processing apparatus generates based on the input inference result to an inference processing apparatus at a subsequent stage of the inference processing apparatus in which the failure has occurred.Type: ApplicationFiled: January 23, 2020Publication date: August 13, 2020Applicant: FUJITSU CLIENT COMPUTING LIMITEDInventors: Yuichiro Ikeda, Masatoshi Kimura, Tomohiro Ishida, Kai Mihara
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Publication number: 20200257994Abstract: An inference processing system includes inference processing devices and performs inference processing such that a succeeding inference processing device performs inference processing to a result of inference processing by a preceding inference processing device.Type: ApplicationFiled: January 23, 2020Publication date: August 13, 2020Applicant: FUJITSU CLIENT COMPUTING LIMITEDInventors: Yuichiro Ikeda, Masatoshi Kimura, Tomohiro Ishida, Kai Mihara
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Publication number: 20200249735Abstract: A charge control apparatus includes a memory and a first hardware processor coupled to the memory. The first hardware processor: acquires, from one or more terminal devices, charge information relating to a charge of the one or more terminal devices; and controls charging of the one or more terminal devices based on the charge information.Type: ApplicationFiled: November 27, 2019Publication date: August 6, 2020Applicant: FUJITSU CLIENT COMPUTING LIMITEDInventor: Tomonori Fujii
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Patent number: 10732786Abstract: A terminal device is provided that has a position determination unit that, when authentication images that capture biological information are to be obtained, determines the position of the next touch location to be displayed in a guide display for touch locations that represent a read operation for the biological information. The determination is made from: the refresh rate of a display that displays the guide display; the number of authentication images to be acquired; and the distance at which the guide display is updated.Type: GrantFiled: June 18, 2019Date of Patent: August 4, 2020Assignee: FUJITSU CLIENT COMPUTING LIMITEDInventors: Masanori Kawahara, Makoto Suzuki, Yukihiro Abiko, Satoshi Semba, Rie Hasada
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Publication number: 20200241988Abstract: An information processing apparatus includes: a plurality of control processing devices and a plurality of information processing devices. The control processing devices control operations compatibly with each other. The information processing devices perform various types of information processing through an interface shared by the control processing devices under control of any of the control processing devices. Before a first control processing device, which controls the information processing devices, is switched to a second control processing device among the control processing device, the second control processing device is set as a copy of the first control processing device. The information processing devices are sequentially switched to be controlled by the second control processing device in a period where the information processing devices do not execute tasks constituting the information processing.Type: ApplicationFiled: December 12, 2019Publication date: July 30, 2020Applicant: FUJITSU CLIENT COMPUTING LIMITEDInventor: Kazuyoshi Toya
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Publication number: 20200243092Abstract: An information processing device includes an acquirer and a registration unit. The acquirer acquires one or more morphemes constituting text data included in a manuscript in a predetermined scene. The registration unit converts a syllable of each of the one or more morphemes into a phoneme and registers the morpheme, the syllable, and the phoneme in a pronunciation dictionary.Type: ApplicationFiled: December 19, 2019Publication date: July 30, 2020Applicant: FUJITSU CLIENT COMPUTING LIMITEDInventor: Yasushi Yabuuchi
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Publication number: 20200233462Abstract: An electronic device includes: a display; a housing including a first cover that covers an end of the display; a panel that is supported by a first face of the first cover and covers the display; and an elastic member that is bonded with the first face, faces a first end face of the panel, extends along the first end face crossing a front face of the panel, and protrudes beyond the front face. The first face is on an opposite side of the display.Type: ApplicationFiled: December 16, 2019Publication date: July 23, 2020Applicant: FUJITSU CLIENT COMPUTING LIMITEDInventors: Shintaro Ohishi, Takashi Abe, Takashi Iijima
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Publication number: 20200233460Abstract: An electronic device includes: a display, a support member, and a fixing member. The display includes: a first face, a second face opposite to the first face, and a lateral face extending between the first face and the second face. The support member includes a support face on which the first face is disposed, and a projection. The fixing member includes a first fixing part fixed to at least one of the second face and the lateral face, and a second fixing part that faces the projection along the first face and is fixed to the support member.Type: ApplicationFiled: November 21, 2019Publication date: July 23, 2020Applicant: FUJITSU CLIENT COMPUTING LIMITEDInventor: Takashi Abe
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Patent number: 10719136Abstract: A resilient element and a keyboard structure are disclosed. The resilient element has a top surface, a dent portion and a conducting post. The dent portion is located on the top surface and has an accommodating space. The conducting post has a post volume and is located beneath the dent portion. When the conducting post is pressed, at least a portion of the post volume enters the accommodating space.Type: GrantFiled: June 22, 2018Date of Patent: July 21, 2020Assignees: CHICONY ELECTRONICS CO., LTD., FUJITSU CLIENT COMPUTING LIMITEDInventors: Fei-Wu Wu, Pin-Fan Chuang, Hideyuki Fujikawa, Naoshige Nishiyama
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Patent number: 10705564Abstract: A housing according to one embodiment includes: a first member being part of an outer wall of the housing; a second member that is another part of the outer wall and includes a first portion overlapping with the first member in a first direction and being joined to the first member via an adhesive agent, and a second portion located at a different position from the first member in a second direction; a first positioning part that is provided at an edge of the first member and projects in the first direction, the edge being located in the second direction; a second positioning part into which the first positioning part is inserted, the second positioning part being provided at the first portion; and a first rib extending from the first positioning part along the edge and being interposed between the first member and the first portion.Type: GrantFiled: May 21, 2019Date of Patent: July 7, 2020Assignee: FUJITSU CLIENT COMPUTING LIMITEDInventor: Takashi Abe
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Publication number: 20200209947Abstract: A system includes: a first platform, a second platform, and a relay device including an expansion bus connected to the first and the second platforms. The relay device includes a power supply control microcomputer that outputs, after having been notified that the first platform is to be restarted, a start request to turn on a power supply of the second platform to the second platform, and starts the communication control microcomputer after the communication control microcomputer is shut down. The second platform includes a second processor that performs shutdown processing to turn off the power supply of the second platform in response to reception of a shutdown request for requesting shutting down of the second platform, and performs start processing for starting the second platform in response to reception of the start request from the relay device.Type: ApplicationFiled: November 27, 2019Publication date: July 2, 2020Applicant: FUJITSU CLIENT COMPUTING LIMITEDInventor: Hiroki Teramoto
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Publication number: 20200210866Abstract: An information processing device includes: a main processor. The main processor receives resource information related to a processing status from each of N processors assuming that N is an integral number equal to or larger than 2, applies the received resource information of the N processors to a computational expression, and calculates processing times corresponding to a processing request from an application for the respective N processors, selects one processor from among the N processors based on the processing times of the N processors, and transmits the processing request to the one processor.Type: ApplicationFiled: November 21, 2019Publication date: July 2, 2020Applicant: FUJITSU CLIENT COMPUTING LIMITEDInventors: Yuichiro Ikeda, Kai Mihara
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Publication number: 20200210254Abstract: An information processing system includes: a plurality of information processing devices each including a processor; and a relay device that connects the information processing devices via an expansion bus and relays communication between the information processing devices. The relay device includes a control unit that represents, for one of the information processing devices, the rest of the information processing devices, and communicates with the one of the information processing devices as an integrated information processing device of the relay device and the rest of the information processing devices.Type: ApplicationFiled: December 26, 2019Publication date: July 2, 2020Applicant: FUJITSU CLIENT COMPUTING LIMITEDInventors: Masatoshi Kimura, Tomohiro Ishida
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Publication number: 20200213231Abstract: An information processing apparatus includes: a memory and a hardware processor coupled to the memory. The hardware processor: monitors progress condition of AI processing in an AI processing device performing the AI processing; outputs data generated by one or more data generating devices to the AI processing device when it is determined that the AI processing device is not congested; and skips output of the data to the AI processing device when it is determined that the AI processing device is congested.Type: ApplicationFiled: November 27, 2019Publication date: July 2, 2020Applicant: FUJITSU CLIENT COMPUTING LIMITEDInventor: Kei Kato
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Publication number: 20200209932Abstract: A system includes: a first platform, a second platform, and a relay device including an expansion bus that connects to the first and the second platforms. The first platform includes a processor that detects an abnormality in communication between the first and the second platforms through the expansion bus. The relay device includes a communication control microcomputer that controls the communication between the first and the second platforms through the expansion bus, and a power supply control microcomputer that controls supply of power from an external power supply to the second platform, and determines, after the abnormality has been detected in the communication between the first and the second platforms through the expansion bus, that the abnormality is caused by one of hardware and software, based on an electrical signal from the second platform, and notifies the first platform of a result of the determination.Type: ApplicationFiled: November 21, 2019Publication date: July 2, 2020Applicant: FUJITSU CLIENT COMPUTING LIMITEDInventor: Hiroki Teramoto
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Publication number: 20200209930Abstract: An information processing apparatus includes: a control device being reset upon receipt of a reset signal; and a control target device controlled by a signal sent from a terminal of the control device. The control device includes a fourth terminal that, when the control device is reset, is disconnected and is required to maintain signals from a connected terminal of the control target device at a high level. The fourth terminal is connected to a source of a second NMOS transistor. A gate of the second NMOS transistor receives a reset signal with which reset is performed at a state of Low. A drain of the second NMOS transistor is connected to a terminal of the control target device. The apparatus further includes a third pull-up resistor that pulls up an electric potential between the drain of the second NMOS transistor and the terminal of the control target device.Type: ApplicationFiled: November 21, 2019Publication date: July 2, 2020Applicant: FUJITSU CLIENT COMPUTING LIMITEDInventor: Akira Takeuchi
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Publication number: 20200210201Abstract: An information processing system includes a plurality of information and a relay device. The information processing devices each includes a processor. The relay device connects the information processing devices via an expansion bus and relays communication between the information processing devices. The relay device includes a power supply controller that controls supply of power to the information processing devices, and performs control to shut off supply of power to the relay device and the information processing devices after detecting shutdown of all the information processing devices.Type: ApplicationFiled: November 15, 2019Publication date: July 2, 2020Applicant: FUJITSU CLIENT COMPUTING LIMITEDInventors: Yuki Kawama, Masatoshi Kimura, Akira Takeuchi, Hiroki Teramoto
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Publication number: 20200209940Abstract: An information processing system includes a plurality of information processing devices, a relay device, and a local area network (LAN) controller. The plurality of information processing devices each include a processor. The relay device connects the plurality of information processing devices via an expansion bus and relays communication between the plurality of information processing devices. The local area network (LAN) controller is operatively coupled to at least one of the plurality of information processing devices and connectable to a LAN. The relay device includes a power supply controller that controls supply of power to the plurality of information processing devices and performs start-up control of the plurality of information processing devices in response to receiving a wake-on-LAN instruction from the LAN via the LAN controller.Type: ApplicationFiled: October 31, 2019Publication date: July 2, 2020Applicant: FUJITSU CLIENT COMPUTING LIMITEDInventor: Shinsuke Murakami