Abstract: The random access memory device of the present invention provides the memory cell array arranged in the form of a matrix. The plurality of memory cells have cross-connected flip-flop circuits. Word driver transistors are provided corresponding to a plurality of word lines, wherein the collector is connected to a high power supply voltage while the emitter is connected to the word line. Moreover, the base of the word driver transistor is connected respectively in common to a selected word line level switching circuit via diodes. The selected word line level switching circuit supplies a current during the write operation to the common connecting point of diodes and forms a current switch together with the diodes. Thus, the voltage of a selected word line is lower than that during the read operation. The present invention provides a random access memory device which has a simplified structure, consumes less current and assures a high speed read operation.

Abstract: A transistor circuit including a pull-down circuit. The pull-down circuit functions to discharge electric charges stored in a base of an output transistor of the transistor circuit and comprises a control transistor, a two-terminal unit (impedance means), and a resistor. The stored electric charges are discharged to ground by way of the two-terminal unit and the resistor. The stored electric charges can be discharged selectively when the output transistor is turned off, with the aid of the control transistor.

Abstract: A semiconductor memory device which includes a plurality of memory cells each having a capacitor, and peripheral circuits of the memory cells, integrated on a semiconductor substrate. Each capacitor has a storage electrode and an electrode opposite to the storage electrode, the opposite electrode being connected to a ground line, wherein, the ground line connected to the opposite electrode of each capacitor is separated from the other ground lines connected to the peripheral circuits. All of the ground lines are connected to a common portion having an impedance lower than the impedance of each ground line, whereby data stored in the capacitors is prevented from being destroyed.

Abstract: A double heterojunction semiconductor laser having a high output power beam of the fundamental transverse mode, which includes a stripe active layer surrounded with clad layers and which has an upper plane and a lower plane, parallel to the upper plane, and sides inclined toward the upper and lower plane, the sides being uneven in a longitudinal direction.

Abstract: A silicon nitride film containing from 20 to 70% oxygen, for use as a surface passivation film, has enhanced ultraviolet ray transmissivity while exhibiting the desirable moisture proofness quality of a silicon nitride film.

Abstract: In a semiconductor memory device including an output buffer circuit receiving data signals read out from a memory cell array, an output stage MOS transistor being turned ON and OFF according to the output signals of the output buffer circuit, and an output buffer enable (OBE) signal generator circuit for generating an OBE signal which is used as the voltage supply to the output stage of the output buffer circuit, a V.sub.BS voltage generator circuit is provided for generating a voltage V.sub.BS higher than the voltage source V.sub.CC preceding the rising up of the OBE signal, which voltage V.sub.BS is used as a voltage supply to the output stage of the OBE signal generator circuit, whereby the OBE signal is formed as a voltage waveform which rises rapidly up to a level higher than the voltage source V.sub.CC.

Abstract: A temperature-compensating voltage generator circuit for compensating the temperature characteristics of an electric device whose electrical characteristics vary in accordance with a change of the ambient temperature and can be changed or controlled by a control voltage. The temperature-compensating voltage generator circuit includes: a temperature-sensing device for generating an electric signal whose voltage level varies in accordance with a temperature change, and a discriminating device for discriminating the electric signal by using a predetermined reference voltage for generating output signals in accordance with the voltage level of the electric signal.

Abstract: A method for producing a semiconductor device which includes forming, in a well having the first conductivity type and selectively provided in a semiconductor substrate having a second conductivity type opposite the first conductivity type, two first impurity diffusion regions having the second conductivity type. In an exposed surface region of the substrate, the two second impurity diffusion regions, respectively, forming, in the well and the exposed surface region of the substrate, a third impurity diffusion region by implanting impurity ions having a P-type or N-type into the semiconductor substrate. The method also includes forming an electric current channel either between the two first impurity diffusion regions or between the two second impurity diffusion regions, thereby forming various integrated circuits by changing the wiring channel.

Abstract: A novel stroke converting mechanism for a push-button switch is disclosed. The stroke converting mechanism is for providing a push-button switch or a keyboard comprising the push-button switches with features such as low cost, low profile, and light and comfortable key touch. The stroke converting mechanism is made from a plate of metal such as 18-8 stainless steel, and fabricated by a single shot of press or by an etching of the plate in a batch process. The delineated plate is then shaped into a specified form by die press. In spite of the simple structure, the stroke converting mechanism can provide a sufficient stroke conversion ratio, e.g., about 4 mm of the key top to a displacement of about 1 mm necessary for actuating a couple of make-break contacts. And also, it reduces the necessary depression force on the key top to a half of the force required for actuating a make-break contacts, and provides a reduction in the height of a push-button switch or a keyboard as much as 3 mm or more.

Abstract: A hollow multilayer printed wiring board and a process for manufacturing the same are provided. The hollow multilayer printed wiring board is comprised of a plurality of printed substrates, superposed upon each other with a predetermined space therebetween. Each of the substrate has a signal conductor pattern formed on at least one surface thereof and a land conductor pattern formed on at least one surface thereof. Each substrate has plated through holes in the land conductor pattern, each of which holes is in line with another plated through hole of at least one of the neighboring substrates to form a continuous through hole or an interstitial through hole. A layer of a low melting point metal is formed at least on the upper and lower end surfaces of each of the plated through holes. This layer serves as a through connection between two or more signal conductor patterns of the substrates and as an interlayer adhesion between the substrates.

Abstract: An ink jet printing head which includes a head body provided with an ink filling port (18), a plurality of rows of nozzles (32A.sub.1 through 32A.sub.5, 40B.sub.1 through 40B.sub.5) arrayed in a staggered formation, pressure chambers (21A.sub.1, 21A.sub.2, . . . , 21B.sub.1, 21B.sub.2, . . . ), one for each of the nozzles, and ink passages (28A.sub.1, . . . , 33A.sub.1, . . . , 38B.sub.1, . . . , 41B.sub.1, . . . ) connecting the ink filling port with the nozzles via corresponding pressure chambers. (19A.sub.1 through 19A.sub.5, 19B.sub.1 though 19B.sub.5). The pressure chambers are formed inside the head body and adjacent to the surface of at least one side of the head body. Piezoelectric elements are mounted on the outside of the head body at positions corresponding to the pressure chambers.

Abstract: A method of producing a semiconductor device, including a bipolar transistor and a Schottky barrier diode (e.g., an SBD transistor), includes the steps of selectively etching an insulating layer formed on an N-type silicon epitaxial layer so as to form an emitter electrode contact window; and forming a polycrystalline silicon layer on the exposed portion of a P-type base region in the window. The method further includes the steps of introducing N-type impurities into the P-type base region through the polycrystalline silicon layer in the window, selectively etching the insulating layer so as to form a base electrode contact window and a contact window for the electrode of the SBD and carrying out a heat treatment for redistribution of the introduced impurities so as to form an emitter region. An emitter electrode is then formed on the polycrystalline silicon layer and the electrode of the SBD is formed directly on the silicon epitaxial layer.

Abstract: In a magnetic disc device, track bytes are added to a record which is to be stored in a cylinder of a magnetic disc in order to utilize additional magnetic disc devices of a different type in the same manner as the first-mentioned magnetic disc device. The magnetic disc device provides track byte check device which checks track bytes read from the record for errors, stores the track bytes in a track byte register when they are correct, and, if the stored track bytes are re-read, utilizes the correct contents stored in the track byte register as the track bytes of the record.

Abstract: An output circuit of a semiconductor device for suppressing erroneous operation due to potential variations of the power supply line or the ground line. The output circuit comprises an output stage inverter connected between the power supply line and the ground line and a clamping circuit for clamping the voltages applied to the output stage inverter. A large instantaneous current which flows through the output stage inverter during a transition of state is greatly suppressed so that erroneous operation is prevented.

Abstract: In a method for inspecting a pattern produced by using pattern data of a predetermined reference pattern, comparison is carried out between the pattern reproduced from the scanning signal of the pattern and the pattern produced from the signal of a modified form of the predetermined reference pattern.

Abstract: A semiconductor device according to the present invention including a first semiconductor region formed on an insulating substrate which is a bit line and, another or second semiconductor region formed on the substrate which is a power supply line. The semiconductor device also includes an opposite conductive type semiconductor region formed on the substrate which is between the two semiconductor regions, additionally includes a metal wiring layer which is a word line and which is situated on an insulating layer on the opposite conductive type semiconductor region. The first semiconductor region bit line is in parallel with the second semiconductor region powerline which is connected to an electric power supply. The metal wiring word line being perpendicular to the second semiconductor region power line which is connected to the electric power supply.

Abstract: A Cu alloy having high resistance to oxidation for use in leads on semiconductor devices is disclosed. The alloy consists essentially of 7-15 wt % Mn, 10-30 wt % Zn, 0.2-10 wt % Ni, 0.1-3 wt % Al, with the balance being Cu and incidental impurities. Also disclosed in a Cu alloy clad material wherein the substrate is made of Cu or Cu alloy having high electrical conductivity and good heat dissipation, and the cladding or partial cladding is composed of the Cu alloy having the composition specified above.

Abstract: An integrated circuit has an input voltage-clamping function and an input current-detecting function. A voltage-clamping circuit is provided for clamping a voltage at the input signal terminal, the voltage being clamped in response to an input current greater than a first predetermined value supplied to the input terminal. A current detecting circuit is also provided for detecting whether the input current supplied to the input terminal is greater than a second predetermined value, whereby the single input terminal for signals is used for both functions, i.e., the input voltage-clamping function and the input current-detecting function.

Abstract: A semiconductor memory device included memory cells each including two PNPN cells cross-coupled with each other, the PNPN cells each including a load transistor and a multi-emitter transistor, the multi-emitter transistor comprising a read/write transistor and a data holding transistor. The read/write transistor has means for decreasing the current amplification factor of the read/write transistor when it operates inversely, whereby the operating speed of the device is improved.

Abstract: A phase-locked loop circuit provides a phase comparator which receives input signals through a first input terminal, a loop filter which receives a first output and a second output of the phase comparator, and a voltage-controlled oscillator which produces output signals of an oscillation frequency proportional to the first output and the second output of the loop filter. The signals corresponding to the output signals produced by the voltage-controlled oscillator are supplied to a second input terminal of the phase comparator so that the phase of the signals supplied to the first input terminal of the phase comparator is compared with the phase of the signals supplied to the second input terminal.