Abstract: Disclosed is a method for exposing an electron beam of a beam-shaping type, wherein the electron beam can be shaped into polygon having desired size by passing through a first and a second apertures. The position of the first or the second aperture tends to be deviated from its design position due to heat, resulting in a deviation of the electron beam. According to the invention, the offset value of the real image formed on the second aperture, with respect to the ideal image, is automatically determined by detecting a current passing through the second aperture. During an electron-beam exposure for patterning, the amount of deflection of the electron beam is corrected by taking the previously obtained offset value into consideration.

Abstract: Disclosed is a semiconductor device having a large number of basic cells, wherein a plurality of basic cells arranged along rows of a semiconductor substrate form a basic cell array and a plurality of the basic cell arrays are arranged along columns of the substrate, and further including spaces formed between each adjoining column. Each basic cell is comprised of first and second P-channel MIS transistors and first and second N-channel MIS transistors. The gates of both the first P-channel and the first N-channel MIS transistors form a first single common gate, and the gates of both the second P-channel and the second N-channel MIS transistors form a second single common gate. The sources or the drains of both the first P-channel and the second P-channel MIS transistors form a first single common source or drain, and the sources or the drains of both the first N-channel and the second N-channel MIS transistors form a second single common source or drain.

Abstract: In the vapor phase epitaxy (VPE) method employed for growth of a compound semiconductor, a high resistivity GaAs buffer layer and a low resistivity GaAs active layer are successively grown on a GaAs substrate in a VPE reaction tube. A GaAs substrate having a crystallographic orientation different from that of the GaAs substrate is positioned just above and opposite to the GaAs substrate, thereby decreasing the epitaxial growth rate and impurities in the epitaxial buffer layer grown on the GaAs substrate. To grow the low resistivity active layer, the dummy substrate is moved away from the GaAs substrate downstream from the gas flow direction. This method provides for a low impurity concentration in the buffer layer and a steep doping distribution between the grown epitaxial layers. Advantageously, the yield of the VPE method is enhanced and the noise figure of FETs produced by this VPE method is decreased.

Abstract: A large scale semiconductor integrated circuit and its wiring method employing a grid system where the layout space is partitioned in the form of a grid by vertical and horizontal line group having an interval larger than a length corresponding to a minimum dimension for a patterning in a manufacturing process; wiring patterns for making connection between each cell which is a unit of layout are depicted on such vertical and horizontal lines; and wirings are made on the basis of the wiring patterns. An interval (d) of these vertical and horizontal lines of the grid is the greatest common factor of the minimum wiring pitches of several overlapped wiring layers and is selected to a dimension which is smaller than said wiring pitch; and the vertical and horizontal line patterns are depicted on the vertical and horizontal lines having the same interval.

Abstract: A dielectric filter in which a plurality of holes are made at predetermined intervals in a dielectric block of small dielectric loss, and a conductor film is formed on the surface of the dielectric block including the interior surfaces of the holes to constitute resonators using the conductor film on the interior surface of each hole as an inner conductor of the resonator and the conductive film on the outer peripheral surface of the dielectric block as an outer conductor, the resonance frequency of the resonators being based on the depth of each hole.

Abstract: An equipment for implanting impurity material ions into a semiconductor wafer which supplies acceleration voltage and which continuously and automatically changes the acceleration voltage within a predetermined range for the purpose of producing impurity layers having a uniform concentration distribution in the direction of the depth of wafer. The equipment is effective in making fine patterns of integrated circuits. In one embodiment, the equipment changes the acceleration voltage continuously so that the frequency of the acceleration voltage is high enough to form a pillar shaped impurity layer at positions in a wafer while the ion beam is irradiated onto the positions respectively thereby to form an impurity layer having a uniform impurity distribution profile.

Abstract: An ECL integrated circuit comprises an emitter-follower transistor at the output stage and a pull-down resistor connected to the emitter-follower transistor. The ECL integrated circuit is provided with a test circuit on a line extending from the output of emitter-follower transistor to a subsequent stage so as to cause a test current to flow only at the time of the test. The test current is smaller than the current usually flowing to the pull-down resistor but larger than the current flowing to the subsequent stage.

Abstract: An MOS device including a substrate bias generating circuit, comprising: a clock generator for receiving an external clock signal and generating first and second internal clock signals; an internal circuit operated by the first and second internal clock signals; a pumping circuit driver for generating third and fourth internal clock signals in synchronization with the first and second internal clock signals and; a pumping circuit operated by the third and fourth internal clock signals. In this device, when the substrate potential (V.sub.BB) is relatively high, currents flow from the substrate to the pumping circuit.

Abstract: In a method of fabricating a semiconductor device having a V-groove insulating isolation structure with polycrystalline silicon filled in the groove of which internal surface is covered with an insulating film of silicon dioxide, the method according to this invention comprises the steps of selectively ion implanting an impurity material into a desired region of the polycrystalline silicon layer in order to give to this region a desired different type of electric conductivity relative to the polycrystalline silicon layer, followed by a selective annealing by an energy beam, such as laser, of a desired part of the polycrystalline silicon layer, including the region into which the impurity material has been ion implanted.

Abstract: A static memory circuit incorporating memory cells of a MOS static type comprising a plurality of potential setting circuits for setting the ground side potential of one selected memory cell to be lower than those of other non-selected memory cells. Thus, reducing power dissipation by reducing current flowing through half-selected and non-selected memory cells without reducing read speed.

Abstract: Disclosed is a semiconductor memory device which comprises a sense amplifier formed on a semiconductor substrate, paired bit lines connected to the sense amplifier and memory cells connected to the bit lines wherein a predetermined bias voltage is applied to the semiconductor substrate and the reading operation is performed by amplifying by the sense amplifier a voltage difference caused between the paired bit lines due to access to the memory cells. This semiconductor memory device is characterized in that a voltage of a phase reverse to a noise transmitted to the bias voltage applied to the semiconductor substrate is applied to the semiconductor substrate through an electrostatic capacitance formed on the semiconductor substrate to cancel the noise. By virtue of this characteristic feature, influences of such noises can be eliminated in the semiconductor memory device of the present invention.

Abstract: A method for producing a bipolar transistor which has no emitter-base short and which attains a high density of integration. The method comprises the steps of forming a polycrystalline silicon layer on an anti-oxidation masking layer formed on a base region, selectively etching the polycrystalline silicon layer to form an opening, introducing impurities into the base region to form an emitter region, converting the polycrystalline silicon layer into an oxide layer whereby the size of the opening is reduced, selectively etching the anti-oxidation masking layer to form an emitter electrode opening, and forming electrodes.

Abstract: A method of exposure used to form circuit patterns of a circuit chip of, for example, a magnetic bubble memory device or a semiconductor IC device whose circuit patterns are composed of a plurality of partially different circuit patterns. In this method, a plurality of projections of a single reticle is effected on a substrate as the substrate is moved by predetermined pitch lengths, and it is possible to form circuit patterns which are different from mere combination of the circuit patterns of the reticle.

Abstract: In order to improve the phase skipping characteristic and the transient response characteristic when using a tracking filter to regenerate the carrier from a PSK signal, a pair of output points having different equivalent noise bandwidths are set by using a first filter having a broad equivalent noise bandwidth and a second filter having a narrow bandwidth. The phase difference between the output points is detected by a phase detector, the phase of the signal at the output point having the broader noise equivalent bandwidth being changed by a phase shifter if a phase difference is detected. The filters and associated circuitry can be connected in either parallel or serial configuration, and the frequency division necessary in the tracking filter can be accomplished in more than one stage to simplify the phase shifting requirement. Additionally either channel switching or polarity inversion of the demodulated baseband signal, or both, can be performed on the basis of such phase differences.

Abstract: A dynamic semiconductor memory device incorporating memory cells of a one-transistor and one-capacitor type is provided with increased charge storage and thus improved read operation. In this device, each of the memory cells is connected to one word line, to one bit line and to one power supply line. The potential of the power supply line is toggled low then high so as to store more charges in the capacitor of a memory cell.

Abstract: A Schmitt trigger circuit has an input-voltage hysteresis characteristic for reducing noise sensitivity and preventing oscillation. In its input stage there is a multi-emitter transistor, and in its output stage a second transistor. The multi-emitter transistor comprises a first emitter and a second emitter. The first emitter is associated with a switching operation in response to the input voltage applied to the base of the multi-emitter transistor. The second emitter is associated with the operation of drawing charges from the base of the second transistor through the base of the multi-emitter transistor to the ground. The use of the multi-emitter transistor prevents the input current from increasing greatly as the input voltage falls.

Abstract: In a semiconductor memory which is provided with a memory cell array, word lines and bit lines for selecting a desired one of memory cells of the memory cell array and a detector circuit for detecting a read current of the selected memory cell, the detector circuit is composed of a pair of transistors having their bases cross-connected so that a hysteresis characteristic is provided by flowing a current in the transistors, and the current is controlled by a hysteresis control circuit to flow only when all word line potentials monitored by the hysteresis control circuit have become lower than a predetermined value, whereby to remove the influence of a noise in the detection of read information of the selected memory cell.

Abstract: A semiconductor integrated circuit device includes a circuit for supplying a reference voltage which is generated in a reference voltage generator circuit to plural load circuits. A plurality of noise limiters have one end commonly connected to the output of the reference voltage generator and another end respectively connected to a corresponding load circuit. The value of the impedance of the noise limiters is of the same order or larger than the output impedance of the reference voltage generator circuit, and capacitors for eliminating the noise may be provided between each noise limiter and each load circuit.

Abstract: Shallow uniform impurity diffusion regions in a semiconductor substrate can be formed through the steps of forming an insulating film having a window on the semiconductor substrate, forming a semiconductor layer on the insulating film and semiconductor substrate exposed at the window, and diffusing a specified impurity from this semiconductor layer into the semiconductor substrate with the melt of semiconductor layer by a high energy beam such as a laser.Simultaneously, the melted semiconductor layer is recrystallized and is used as a contact electrode having a low resistance and extending from the impurity diffusion region. Diffusion of the impurity into the semiconductor layer, which is the impurity diffusion source, can be performed at the time of forming the semiconductor layer or after the formation of the semiconductor layer.

Abstract: An oscillation circuit for providing an oscillation output having a duty ratio different from 50%. The oscillation circuit is adapted to control, for example, a bootstrap circuit included in an EPROM which is erasable by means of ultraviolet rays. The oscillation circuit is comprised of a depletion type MOS transistor used as a resistance in each CR time constant circuit; the gate and the drain or the gate and the source of each depletion type MOS transistor being connected together and the oscillation circuit comprising a delay circuit having its output positively fed back to its input.