Patents Assigned to Fujitsu Limited
  • Publication number: 20140173163
    Abstract: An information processing apparatus includes a first processor, a second processor, a switch configured to relay a packet transmitted between the first processor and the second processor, a first output buffer corresponding to the first processor and being configured to store therein a first packet from the first processor and being addressed to the second processor and received through the switch, a first input buffer corresponding to the first processor, and a first selector configured to select one of a first path and a second path, based on a free space of the first output buffer. When the first packet is input, the first path is configured to output the first packet from the first processor to the switch through the first input buffer and the second path is configured to output the first packet from the first processor to the switch not through the first input buffer.
    Type: Application
    Filed: February 24, 2014
    Publication date: June 19, 2014
    Applicant: FUJITSU LIMITED
    Inventor: Yoshihiro KITAHARA
  • Publication number: 20140173101
    Abstract: A calculator includes communication devices, a detection unit, and a communication control unit. The detection unit performs communication among the plurality of communication devices connected to the same segment in a network, to thereby detect division of a network connected to each communication device. In the case division of the network is detected by the detection unit, the communication control unit generates information about a correspondence relationship between each communication appliance and an appliance in a reachable network. The communication control unit performs communication between a communication device and an appliance in a network based on the information about a correspondence relationship.
    Type: Application
    Filed: December 4, 2013
    Publication date: June 19, 2014
    Applicant: FUJITSU LIMITED
    Inventor: Takahiro SAYAMA
  • Publication number: 20140169264
    Abstract: A base station apparatus includes a plurality of wireless control devices, each of which transmits data blocks addressed to a wireless device connected to the wireless control device, a plurality of wireless devices, each of which transmits data blocks addressed to a wireless control device connected to the wireless device; and relay devices arranged between the wireless control devices and the wireless devices. Each relay device includes a plurality of transmission ports, a table to store a correspondence between destinations of received data blocks and transmission ports for transmitting the reception data blocks, a sorting unit to sort received data blocks to one of the plurality of transmission ports corresponding to destinations of the received data blocks, and a controller to control rewriting of the table for changing the correspondence.
    Type: Application
    Filed: October 28, 2013
    Publication date: June 19, 2014
    Applicant: FUJITSU LIMITED
    Inventor: MASATO KATORI
  • Publication number: 20140167844
    Abstract: A distortion compensation device includes: a distortion compensator configured to output, to a power amplifier, a predistortion signal obtained by performing distortion compensation processing on a transmission signal by using a distortion compensation coefficient, wherein the distortion compensator limits bands of a reference signal and a feedback signal so that the bands fall in a pass band and updates the distortion compensation coefficient based on an error between the reference signal and the feedback signal, the reference signal corresponding to the predistortion signal, the feedback signal corresponding to an output feedback of the power amplifier.
    Type: Application
    Filed: October 17, 2013
    Publication date: June 19, 2014
    Applicant: FUJITSU LIMITED
    Inventors: Yuichi UTSUNOMIYA, Hiroyoshi ISHIKAWA, Toshio KAWASAKI, Alexander Nikolaevich LOZHKIN, Kazuo NAGATANI
  • Publication number: 20140169283
    Abstract: A method is provided for managing wireless network traffic that includes designating a first resource block of a macro base station and a second resource block of a small cell base station for access by a physical random access channel (PRACH). The method further includes designating a first random access subframe associated with the first resource block and a second random access subframe associated with the second resource block for access by a random access channel message. The first random access subframe has a first allocation of random access signatures that are configured to receive a plurality of random access requests. The second random access subframe is time-aligned with the first random access subframe and has a second allocation of random access signatures that are configured to receive a plurality of random access requests.
    Type: Application
    Filed: December 19, 2012
    Publication date: June 19, 2014
    Applicant: FUJITSU LIMITED
    Inventors: Dorin Gheorghe Viorel, Chenxi Zhu, Akira Ito
  • Publication number: 20140168259
    Abstract: An image processing device includes: a processor; and a memory which stores a plurality of instructions, which when executed by the processor, cause the processor to execute, acquiring an image to be displayed including a two-dimensional code and a positioning pattern superimposed, wherein the two-dimensional code defines information to be displayed on the basis of an image pattern including a first pixel value and a second pixel value, wherein the positioning pattern defines reference coordinates to display the information to be displayed; extracting the two-dimensional code from the image, using a first color component to extract a pixel value identified as the first pixel value and a pixel value identified as the second pixel value; and extracting the positioning pattern from the image using a second color component that identifies as identical to the first pixel value both pixel values that are identified as the first and second pixel values.
    Type: Application
    Filed: September 27, 2013
    Publication date: June 19, 2014
    Applicant: FUJITSU LIMITED
    Inventor: Nobuyasu Yamaguchi
  • Publication number: 20140170784
    Abstract: A method of manufacturing a photoelectric composite substrate, includes: aligning and fixing an optical element having a solder terminal to an optical waveguide for forming a path of an optical signal on a printed circuit board; mounting the optical waveguide, to which the optical element is fixed, on the printed circuit board; and welding the solder terminal to an electrode of a package installed on the printed circuit board or an electrode of the printed circuit board.
    Type: Application
    Filed: September 18, 2013
    Publication date: June 19, 2014
    Applicant: FUJITSU LIMITED
    Inventors: Tetsuro YAMADA, Akiko MATSUI, Yoshiyuki HIROSHIMA, Takahiro OOI, Kohei CHORAKU
  • Publication number: 20140170965
    Abstract: A base station arranged to operate in a wireless communications system as a booster base station providing a cell which is operable as a booster cell providing additional capacity to a coverage cell which it at least partially overlaps, the booster cell being operable to function in a first mode and a second mode, wherein the booster cell provides more additional capacity to the coverage cell when functioning in the first mode than it does when functioning in the second mode, the booster base station comprising: a listening module configured to perform a survey of the uplink interference received at the booster base station; a storage module configured to store uplink scheduling information; a calculation module configured to calculate an adjusted uplink interference; and a switching module configured to switch the booster cell from functioning in the second mode to functioning in the first mode.
    Type: Application
    Filed: September 26, 2013
    Publication date: June 19, 2014
    Applicant: FUJITSU LIMITED
    Inventors: Zhaojun LI, Paul BUCKNELL, Timothy MOULSLEY, Yoshihiro KAWASAKI
  • Publication number: 20140173120
    Abstract: A method for establishing a communication between a plurality of computers and a data processing device through a network, the method including: reporting, when a change occurs in a communication state between the plurality of computers and the data processing device, the change in the communication state to another computer; recognizing, from among the plurality of computers, a computer which establishes a communication with the data processing device, based on a notice of the change in the communication state; and establishing, when a number of computers for which each of the plurality of computers recognizes to have established a communication with the data processing device is not greater than a predetermined prescribed number, a communication with the data processing device, with a request from the data processing device.
    Type: Application
    Filed: February 19, 2014
    Publication date: June 19, 2014
    Applicant: FUJITSU LIMITED
    Inventor: Hiroshi Noda
  • Publication number: 20140172369
    Abstract: A computer-readable recording medium stores therein an abnormality cause estimating program causing a computer to execute a process. The process includes acquiring load information of a system; determining whether or not the system indicates abnormality based on the load information, and specifying a first function group which includes one or a plurality of functions executed by the system when the determination indicates that the system indicates the abnormality and specifying a second function group which includes one or a plurality of functions executed by the system when the determination indicates that the system does not indicate abnormality; and outputting information of a function which is not included in the second function group among the functions included in the first function group.
    Type: Application
    Filed: October 3, 2013
    Publication date: June 19, 2014
    Applicant: FUJITSU LIMITED
    Inventors: Hideya IKEDA, Nobuhiko Fukui, Minoru Yamamoto
  • Publication number: 20140172367
    Abstract: An interference check apparatus that includes: a memory configured to store a latest edit time stamp related to at least one of a profile or a position for each of the plurality of components, and to store an edit time stamp for each of the plurality of components at an interference check execution time and to store an interference check data representing an execution result of an interference check between components out of the plurality of components; and a processor configured to execute a procedure, the procedure comprising: determining a validity of the interference check data stored based on the latest edit time stamp of each of the plurality of components and the edit time stamp of components when the interference check is executed contained in the interference check data.
    Type: Application
    Filed: October 3, 2013
    Publication date: June 19, 2014
    Applicant: FUJITSU LIMITED
    Inventors: Yoshihito OKUWAKI, Kenji ISHIZUKA, Akio SAKAMOTO, Youji UCHIKURA, Kazuhiko HAMAZOE, Yoshikazu ICHIKAWA
  • Publication number: 20140169694
    Abstract: An image processing apparatus includes a calculation section configured to calculate filtering coefficients of a filter with a first area in an image that is partitioned into multiple first areas including the first area, the image being partitioned differently into multiple second areas, each one of which being covered by several first areas, to calculate a convoluted image of a second area using the filtering coefficients calculated with the first areas covering a part of the second area, the calculation being executed for the several first areas covering distinct parts of the second area, respectively; and an interpolation section configured to interpolate a pixel in the second area using pixels at the same position in the convoluted images of the second area which are convoluted with the respective filtering coefficients.
    Type: Application
    Filed: September 24, 2013
    Publication date: June 19, 2014
    Applicant: FUJITSU LIMITED
    Inventors: Hiroyasu YOSHIKAWA, YUKIO HIRAI
  • Publication number: 20140173237
    Abstract: A storage device includes a memory including a first storage area configured to store area information that indicates a geographical area, and a second storage area configured to store data, and a processor coupled to the memory and configured to append data storage information, which indicates a location of the storage device, to the data to be stored in the second storage area, and allow a piece of the data stored in the second storage area to become available, the piece having the data storage information indicating that the location of the storage device falls within an area indicated by the area information, while the storage device is located within the area indicated by the area information.
    Type: Application
    Filed: December 2, 2013
    Publication date: June 19, 2014
    Applicant: FUJITSU LIMITED
    Inventors: Ayumi TAKANO, Toru IRISAWA, Shigeru IKUSHIMA, Takuma YAMADA
  • Publication number: 20140169379
    Abstract: A disclosed relay apparatus includes: a generator that generates, upon receipt of a first packet that includes a first identifier of a virtual machine that is newly executed in an information processing apparatus connected to the relay apparatus from the information processing apparatus, a second packet that includes a second identifier of the virtual machine, which is different from the first identifier, and requests to set relay for the virtual machine; and a processing unit that sets the relay for the virtual machine by using the second identifier of the virtual machine, which is included in the second packet generated by the generator or received from the information processing apparatus.
    Type: Application
    Filed: October 30, 2013
    Publication date: June 19, 2014
    Applicant: FUJITSU LIMITED
    Inventors: Kazuki HYOUDOU, Yukihiro Nakagawa, Takeshi Shimizu
  • Publication number: 20140167824
    Abstract: A quantizer takes an analog signal as input and produces a quantized signal for output. The quantizer includes a shoot-through current detection unit and a feedback unit. The shoot-through current detection unit is configured to detect a shoot-through current flowing through the quantizer. The feedback unit is configured to feed back a signal from the shoot-through current detection unit and control an electric charge stored at an input of the quantizer.
    Type: Application
    Filed: November 8, 2013
    Publication date: June 19, 2014
    Applicants: FUJITSU SEMICONDUCTOR LIMITED, FUJITSU LIMITED
    Inventors: Hiroyuki NAKAMOTO, Hideta OKI
  • Publication number: 20140173337
    Abstract: A storage-apparatus has a plurality of storage-devices and a controller for controlling data read from and write to the plurality of storage-devices, the controller includes a determination-unit and a restore-processing-unit, when a new storage-device has failed in a non-redundant state being a redundant group state without redundancy, in which some of the storage-devices had failed out of the plurality of storage-devices, the determination-unit configured to determine whether execution of compulsory restore of the redundant group is possible or not on the basis of a failure cause of the plurality of failed storage-devices, and if the determination unit determines that the execution of compulsory restore of the redundant group is possible, the restore-processing-unit configured to incorporate a plurality of storage-devices including a newly failed storage-device in the non-redundant state into the redundant group and to compulsorily restore the storage-apparatus to an available state.
    Type: Application
    Filed: November 6, 2013
    Publication date: June 19, 2014
    Applicant: FUJITSU LIMITED
    Inventors: Atsushi IGASHIRA, Hidefumi KOBAYASHI
  • Publication number: 20140173416
    Abstract: In a wireless terminal, a processor determines a reference object, as a display reference in a specified Web page, in accordance with a correspondence relationship between objects, which are included in the specified Web page and are each linked to other Web pages, and the frequency of past selection of each object. The processor then maps the specified Web page in a display memory, searches the specified Web page mapped in the display memory for the reference object, and sets a display window including the reference object, which has been searched for, in the display memory.
    Type: Application
    Filed: September 24, 2013
    Publication date: June 19, 2014
    Applicant: FUJITSU LIMITED
    Inventors: Ken NAKAMURA, Katsuaki AKAMA
  • Publication number: 20140169442
    Abstract: A clock data recovery method includes: integrating an input data signal over a number of cycles of a sample clock to generate an integrated signal; performing a digital process on the integrated signal to output a first digital signal; interpolating the first digital signal in accordance with phase information to generate interpolation data; outputting phase difference data indicating a difference in phase of the interpolation data from the sample clock; performing a filtering process on the phase difference data to generate the phase information; performing an equalization process on the interpolation data in accordance with output data; and performing a binary decision on results of the equalization process to generate the output data.
    Type: Application
    Filed: September 20, 2013
    Publication date: June 19, 2014
    Applicant: FUJITSU LIMITED
    Inventors: Takushi HASHIDA, Hirotaka Tamura
  • Publication number: 20140169782
    Abstract: A network design apparatus includes: a first processing unit configured to select one or more paths between nodes in response to a request for a bandwidth between pairs of nodes in a network to determine working communication routes and protecting communication routes connecting the pairs of nodes, and estimate a number of communication lines in the selected path; and a second processing unit configured to allocate logical channels of the communication lines to the working communication routes and the protecting communication routes based on the requested bandwidth, wherein the first processing unit determines the protecting communication routes while permitting the sharing of the path, and the second processing unit allocates a common logical channel to one or more communication routes, out of the protecting communication routes, that share the path and are not simultaneously used when a failure occurs in the working communication routes.
    Type: Application
    Filed: September 4, 2013
    Publication date: June 19, 2014
    Applicant: Fujitsu Limited
    Inventors: Tomohiro HASHIGUCHI, KAZUYUKI TAJIMA, Yutaka TAKITA
  • Publication number: 20140173540
    Abstract: A circuit design support method that is executed by a computer, includes calculating a first performance value of a circuit under design before a layout process, by inputting into a first function model that represents a performance value of the circuit under design before the layout process, the values of parameters among parameters of a second parameter group and corresponding to parameters of a first parameter group; acquiring a second performance value that is of the circuit under design after the layout process and obtained by simulating operation of the circuit under design after the layout process, using the values of the parameters of the second parameter group; and generating based on the calculated first performance value, the acquired second performance value, and the second parameter group, a second function model that represents a difference in the performance value of the circuit under design before and after the layout process.
    Type: Application
    Filed: October 29, 2013
    Publication date: June 19, 2014
    Applicant: FUJITSU LIMITED
    Inventor: YU LIU