Abstract: An address buffer for a dynamic memory includes a flip-flop. The flip-flop is coupled at its one input/output terminal with both a first input circuit and a third input circuit connected in parallel with each other and at its other input/output terminal with a second input circuit. The second input circuit receives a reference voltage and is activated by an external address timing clock during a normal operation mode. The first input circuit is also activated by the external address timing clock, but receives an external address. The third input circuit receives an internal refresh address and is activated by an internal refresh address. The address buffer cooperates with a switcher which produces the internal refresh address timing clock and the external address timing clock, alternatively, by switching a basic timing clock generated by an address drive clock generator.

Abstract: A recognition apparatus comprising an image sensor sensing an image of a pad pattern on an IC chip pattern, a pre-treatment circuit for converting the outputs of the image sensor into binary-coded signals in accordance with at least two slice levels, and a pattern detecting section for detecting the position and inclination of the pad pattern based on the images of the pad and chip patterns corresponding to the data stored in a memory; that is, the binary-coded signals generated in accordance with two slice levels. Two image sensors may be used for sensing the chip and pad data respectively.

Abstract: A comb-line type dielectric filter in which a plurality of resonator holes are made in a dielectric block at predetermined intervals and coupling adjustment holes are made between the resonator holes, the interior surfaces of the resonator holes and the surface of the dielectric block being entirely or partly covered with a conductor film. The coupling adjustment holes are disposed apart from the line joining the centers of the resonator holes, and a coupling adjusting member made of metal or dielectric material is inserted into each coupling adjustment hole.

Abstract: A bias-voltage generator suitable for measuring a substrate leakage current is disclosed. The bias-voltage generator comprises of an oscillator, a charge-pumping circuit which is driven by the oscillator via a pumping capacitor, and a charge-pumping switch. The charge-pumping switch is connected in series with the charge-pumping circuit. The charge-pumping switch cooperates with an external electrode for controlling the ON or OFF condition of the charge pumping circuit. The charge-pumping switch is turned OFF by the external electrode becoming a floating state and a resistor employed to ensure the charge pumping switch is inoperable after the above-mentioned measurement is completed and the circuit is shipped from the factory.

Abstract: A system and method for evenly heating semiconductor wafers in a horizontal elongated reaction tube, wherein a furnace surrounding only a part of the length of the reaction tube is caused to move so as to pass along each wafer placed in the reaction tube. The system is especially useful for processing wafers at high temperatures for a short period of time.

Abstract: A fundamental logic circuit used, for example, in an electronic computer, comprising an output inverter transistor and a switching transistor which discharges a base charge stored in a storage capacitance in a base-emitter junction of the output inverter transistor when the output inverter transistor changes from the turned on condition to the turned off condition.

Abstract: In a buffer circuit comprising a first, a second and a third transistor and a capacitor for bootstrap action, an inverter is connected to the output point at which the second and third transistors are connected in series, the inverter inverting the potential of the output point and supplying the inverted potential to the gate of the first transistor, thereby ensuring the quick rise of the leading edge of the output signal.

Abstract: An input protection circuit which protects the gate of a MIS transistor from breakdown due to an excessively high voltage being applied thereto. The input protection circuit includes a first resistor and a second resistor connected in series between a input terminal and a gate of the MIS transistor, a first protection transistor provided between a first connecting point between the first and second resistors and one side of the power supply, and a second protection transistor provided between a second connecting point between the second resistor and the gate of the MIS transistor the other side of the power supply. The first protection transistor has a large mutual conductance gm, while the second protection transistor has a low breakdown voltage.

Abstract: A semiconductor device is used, for example, for controlling and driving thermal heads of a facsimile apparatus and includes a first circuit activated when power is supplied to the semiconductor device and a second circuit activated only when both power and a power control signal are applied to the semiconductor device. The semiconductor device further includes a power switch circuit which includes a semiconductor electronic circuit and which supplies power to the second circuit only when the power control signal is applied thereto.

Abstract: A semiconductor read only memory device comprises bit lines, word lines, a load transistor, a multiplexer including a plurality of transistors, and a memory cell array in which each memory cell has one transistor having a gate connected to one of the word lines and corresponding to one of the bit lines connected to the transistors of the multiplexer. A gate transistor is inserted between the load transistor and the multiplexer, and a gate voltage control circuit, for selectively providing a higher level signal and a lower level signal, is connected to the gate transistor.

Abstract: A semiconductor circuit used as a buffer circuit having an input stage circuit for receiving an input clock signal and an inverted input clock signal, a bootstrap circuit including a transistor for receiving the output of the input stage circuit and for maintaining the gate voltage of the transistor at a high level during the standby period, and an output circuit, including a transistor which is switched on and off by the output of the bootstrap circuit, for generating an output clock signal; the semiconductor circuit further comprising a current leak circuit for maintaining, during the standby period, the voltage of a point in the semiconductor circuit which is charged during the standby period at the value corresponding to the voltage of the power source, whereby the delay of the output clock signal, caused of the fluctuation by the voltage of the power supply during the standby period, is improved and then the high speed access time in the dynamic memory is carried out.

Abstract: Electronic communication device shelf units for packing therein printed circuit boards wherein the shelf units are to be put one upon another in a cabinet, wherein each said shelf unit comprises hollow side plates provided with air inlet openings on their outer faces, and a top plate which is connected to the side plates and having a V-shaped heat diffusion plate defining thereon an air introduction space; the side plates are provided, on their inner faces, with openings communicating with the air introduction space, such that hot air diffusion for each shelf unit is independent of the other shelf units.

Abstract: A crossover construction of a thermal-head is which the thermal-head comprises: a substrate of insulating material; a plurality of heat elements disposed side by side in one row on said substrate; a plurality of lower thin film conductor patterns each of which connects to each of said heat elements and extends in direction X; an insulating layer disposed over said lower conductors; a plurality of upper conductor patterns disposed in parallel in another direction Y on said insulating layer so as to form a crossover on said substrate, said upper and lower conductors being selectively connected together through openings of said insulating layer, wherein said insulating layer and said upper conductors comprise printed and cured paste of insulating material and conductive material, respectively, each paste being of the low temperature curing type which can be cured at a temperature low enough not to affect the resistance of said thin film lower conductors, and a metallic layer of low resistance is coated on each o

Abstract: In a decoder circuit in which a transistor for reducing power use, which is supplied at its gate with a first control signal, is connected in series with a logical gate composed of a load transistor and a plurality of transistors which are respectively supplied at their gates with address signals, there is provided an off buffer circuit which comprises a first inverter for receiving the output of the logical gate and a second inverter for receiving the output of the first inverter. To a load transistor of the second inverter is provided a second control signal delayed in phase behind the first control signal and the output of the off buffer circuit is used as a decoded output of the address signal, so that the rise and fall of a word line is reduced.

Abstract: A clamping transistor is connected to a signal input terminal of a signal processing circuit, such as a microprocessor, which operates on the output voltage from a stabilized power source circuit. When the output voltage from the stabilized power source circuit is below a predetermined value at the time of turning ON or OFF a power source switch, the clamping transistor is held in the ON state, thereby preventing the application of an input signal of a level higher than the power source voltage of the signal processing circuit, to the signal input terminal of the signal processing circuit.

Abstract: A MIS device including a substrate bias generating circuit comprising: an oscillating circuit for generating clock signals; a pumping circuit comprised of a charging and discharging circuit and a bias circuit, for absorbing charges in a semiconductor substrate, and; a clamp circuit for clamping the potential of the substrate at a desired level.

Abstract: An improved positive-working resist material capable of forming on a substrate either a positive resist pattern or a negative resist pattern. The positive-working resist material comprises a positive-working resist resin having incorporated therein one or more photochromic compounds, such as spiropyrans, triphenylmethane dyes, anils and the like. A positive or negative resist pattern having a remarkably improved definition can be obtained. The use of such a positive-working resist material in the formation of a negative resist pattern on the substrate is also disclosed.

Abstract: A current stretch detection method for a bubble device in which bubbles are written at least one bit apart. A stretch pulse is applied to a stretch conductor so that when a bubble is detected, it is maintained stretched, even though the bubble following it has moved one bit. Preferably the stretch pulse is of a convex-shape. A bubble device has a hairpin stretch conductor and a detecting element disposed centrally in the conductor. The terminal of the detecting element on the higher potential side is arranged so that it does not cross the stretch conductor. The contiguous propagation pattern is provided with a notch at a position in which the stretch conductor is located.

Abstract: A multi-input logic circuit comprises a multi-emitter transistor having emitters which are connected to a logic input terminals of the multi-input logic circuit, a PNP type transistor having a base which is connected to a collector of said multi-emitter transistor and a level shift element which is connected to an emitter of the PNP type transistor. This arrangement facilitates the maintenance of an improved margin of threshold voltage to input voltage.

Abstract: The present invention relates to a digital phase locked loop circuit, particularly to a circuit which realizes accurately digital phase locked loop pull-in operation at a high speed with a simplified circuit structure.In the present invention, in order to obtain a phase difference between a single frequency signal and the digital phase locked loop clock signal which is obtained by dividing a specified frequency signal with a dividing counter, the phase difference is obtained in accordance with the signs, absolute values and amplitude ratio of two adjacent sample values. The sample values of said single frequency signal are taken at two points based on said digital phase locked loop clock signal corresponding to a phase difference of .pi./2 radians of said single frequency signal. A fast pull-in of the digital phase locked loop is realized by setting a value corresponding to the obtained phase difference into a dividing counter.