Abstract: A design supporting method includes partitioning a partition path of circuit information into partitioned paths based on a given condition, calculating a variation value of each of the partitioned paths based on variation values on a delay of a cell included in the corresponding partitioned path, calculating a partition propagation delay time of each of the partitioned paths based on the variation value of the corresponding partitioned path, and calculating a source propagation delay time of the source path by merging the propagation delay time of each of the partitioned paths.

Abstract: An interface apparatus that transmits and receives data to and from another node coupled via a bus cable includes a port coupled to a port of the another node through the bus cable, a connection management state machine which corresponds to the port and changes the port from an active state to an inactive state when a synchronism of the port is lost, a state transition suppression circuit which generates a state transition suppression signal to suppress the change of the port from the active state to the inactive state, and a synchronization state machine that starts a resynchronization of the port in the active state based on the detection of the synchronism of the port being lost.

Abstract: An image processing circuit includes a memory configured to store an image retrieved from an image pick-up element, wherein the image is written on a plurality of rows of a two dimensional storage area of the memory and a filtering circuit configured to perform a filtering process with respect to each pixel data on a row when the image is written on the plurality of rows of the two-dimensional storage area of the memory.

Abstract: A level shifter unit outputting a level shifted signal generated by level shifting of output signals of the first and second differential amplifier circuits, and an output circuit including complementary output transistors series being coupled between the high potential power supply and the low potential power supply and inputting the level shifted signal.

Abstract: An internal voltage generator when activated, generates an internal voltage to be supplied to an internal circuit. Operating the internal voltage generator consumes a predetermined amount of the power. In response to a control signal from the exterior, an entry circuit inactivates the internal voltage generator. When the internal voltage generator is inactivated, the internal voltage is not generated, thereby reducing the power consumption. By the control signal from the exterior, therefore, a chip can easily enter a low power consumption mode. The internal voltage generator is exemplified by a booster for generating the boost voltage of a word line connected with memory cells, a substrate voltage generator for generating a substrate voltage, or a precharging voltage generator for generating the precharging voltage of bit lines to be connected with the memory cells.

Abstract: A semiconductor device includes a CPU core circuit, a bus connected to the CPU core circuit, and a memory BIST circuit configured to perform a memory test in response to an instruction supplied from the CPU core circuit through the bus.

Abstract: An analog-to-digital converter (ADC) operates repetitively to perform a series of conversion cycles. A comparator (9) receives an analog input signal (V.sub.IN) and compares it with an analog comparison signal produced by a digital-to-analog converter (5). A successive-approximation register circuit (22) holds a digital trial signal value and uses it to control the value of the analog comparison signal in each conversion cycle so as to perform up to two comparisons per cycle, thereby to produce digital data that has a first value ("+1") when the input signal value is greater than a first comparison value (V.sub.C1) and that has a second value ("-1") when the input signal value is less than a second comparison value (V.sub.C2) and that in all other cases has a third value ("0"). The first comparison value (V.sub.C1) is set higher than the trial signal value determined for use in the cycle concerned, and the second comparison value is set lower than that trial signal value.