Patents Assigned to Fujitsu Microelectronics Europe, GmbH
  • Patent number: 6904112
    Abstract: A method for modulating a basic clock signal for digital circuits, in which distances between adjacent switching edges are altered, the basic clock signal being conducted via a changing number of delay units for altering the distances between the adjacent switching edges, the method comprising the step of calibrating delay times of the delay units (D1-Dn), wherein the delay units (D1-Dn) each have a plurality of delay elements (10) which are controlled to impart zero delay or a non-zero value of delay to a clock signal individually or in groups of the display elements; wherein the respective distance between two adjacent switching edges is derived from numbers of a random number generator; and wherein the distance between two successive switching edges is derived as a function of the random number and a modulation factor.
    Type: Grant
    Filed: July 17, 2000
    Date of Patent: June 7, 2005
    Assignees: Mannesmann VDO AG, Fujitsu Microelectronics Europe, GmbH
    Inventors: Frank Sattler, Walter Klumb
  • Patent number: 6741660
    Abstract: In a method for modulation of a basic clock for digital circuits, in which the intervals between adjacent switching edges are varied, with the basic clock being split into equidistant sections, and the intervals between adjacent switching edges being varied as a function of cyclically recurring random numbers, the position of a switching edge (ai+1) following a switching edge (a1) to be calculated as follows: a i + 1 = ( a 1 + p - ( N - 1 2 - Z i + 1 ) ) ⁢   ⁢ m
    Type: Grant
    Filed: July 13, 2000
    Date of Patent: May 25, 2004
    Assignees: Mannesmann VDO AG, Fujitsu Microelectronics Europe GmbH
    Inventors: Frank Sattler, Walter Klumb
  • Patent number: 6163283
    Abstract: Coding circuitry (34), for use for example in selecting cells of a cell array in a digital-to-analog converter, produces first and second sets of thermometer-coded output signals in dependence upon a binary input signal. As the input signal increases progressively in value from a first value to a second value, the first-set output signals (COLA) are activated in a predetermined sequence and the second-set output signals (COLB) are deactivated in a predetermined sequence. As the input signal increases progressively in value from the second value to a third value, the first-set output signals are deactivated in a predetermined sequence and the second-set output signals are activated in a predetermined sequence.Such coding circuitry reduces the numbers of output signals that change in response to changes in the input-signal value.In another embodiment (FIG. 12) the coding circuitry includes respective row, column and depth decoders (58, 56, 54).
    Type: Grant
    Filed: January 8, 1999
    Date of Patent: December 19, 2000
    Assignee: Fujitsu Microelectronics Europe GmbH
    Inventor: William George John Schofield
  • Patent number: 6100830
    Abstract: Differential switching circuitry, for use for example in a digital-to-analog converter, includes: a first switch element (S1) connected between a common node (CN) and a first output node (OUT1), and a second switch element (S2) connected between the common node (N) and a second output node (OUT2). First and second driver circuits (12, 14) correspond respectively to the first and second switch elements, each driver circuit switching its corresponding element ON and OFF in dependence upon an applied input signal (IN1, IN2). The driver circuits co-operate such that one switch element is ON when the other is OFF. Each switch element (S1, S2) is paired with a matching element (46, 44) in the other switch element's driver circuit. That matching element (e.g. 44) is coupled operatively to its paired switch element's driver circuit (14) and is matched, e.g.
    Type: Grant
    Filed: January 8, 1999
    Date of Patent: August 8, 2000
    Assignee: Fujitsu Microelectronics Europe GmbH
    Inventor: Ian Juso Dedic