Patents Assigned to Fujitsu Microelectronics, Inc.
  • Patent number: 6362652
    Abstract: An input circuit allows input buffers fabricated using submicron CMOS technologies to receive input signals having a voltage swing of 5V. The input circuit uses a cascode transistor to bias the drain of the input transistor so that the VGD of the input transistor does not reach or exceed the gate-oxide breakdown voltage. Outputs of the input buffers have a maximum voltage that is limited by their respective supply voltages.
    Type: Grant
    Filed: December 20, 1999
    Date of Patent: March 26, 2002
    Assignee: Fujitsu Microelectronics, Inc.
    Inventors: Mustafa Ertugrul Oner, Sumer Can
  • Patent number: 6128406
    Abstract: A method of compressing a block of graphics image data into a compressed block operates on uncompressed bitmap image data to generate a compressed representation of the image. It also operates on compressed bitmap image data to generate the original, uncompressed representation. To compress an image, all 8 pixel by 8 pixel blocks of the image are individually processed in sequence. For each block, all distinct colors present in the block are identified and assigned an ordinal number. A data structure for the block is generated to store the number of distinct colors present in the block, a compression image quality mask value, the actual RGBA quadruplet for each color present in the block, and for each distinct color, sets of group and line binary flags indicating the presence of a particular color at a particular pixel within the block. The data structure for the block is then stored in memory or in a computer file and the next block of the image is processed.
    Type: Grant
    Filed: April 30, 1997
    Date of Patent: October 3, 2000
    Assignee: Fujitsu Microelectronics, Inc.
    Inventor: Alex Ostrovsky
  • Patent number: 6091850
    Abstract: A method of compressing and decompressing graphics images. The compression method operates on uncompressed bitmap image data to generate a compressed representation of the image. To compress an image, all 8 pixel by 8 pixel blocks of the image are individually processed in sequence. For each block, all distinct colors present in the block are identified and assigned an ordinal number. Two pixel colors are deemed distinct if the difference between the colors is greater than an epsilon value. The epsilon value is a function of the total brightness of the block. A data structure for the block is generated to store the number of distinct colors present in the block, the actual RGBA quadruplet for each distinct color, and a color ordinal number of each pixel in the block representing the distinct color of the pixel. To decompress the image, the RGBA quadruplets of all pixels within each block are reconstructed from the data structure for the block.
    Type: Grant
    Filed: September 24, 1998
    Date of Patent: July 18, 2000
    Assignee: Fujitsu Microelectronics, Inc.
    Inventor: Alex Ostrovsky
  • Patent number: 5661411
    Abstract: A logic circuit employing feedback controlled loads to increase the response time and minimize power consumption. A plurality of input circuits are provided, each having means for coupling a first signal to a second signal. A first load responsive to the second signal provides a means for pulling up the first signal and a second load responsive to the first signal provides a means for pulling down the second signal. A driver responsive to the first and second signals is provided for generating an output voltage.
    Type: Grant
    Filed: January 5, 1996
    Date of Patent: August 26, 1997
    Assignee: Fujitsu Microelectronics, Inc.
    Inventor: Huy S. Nguyen
  • Patent number: 4584653
    Abstract: A method for manufacturing a gate array IC device in which the turn-around time on design is short, the system design is simple, and the memory area for designing is reduced. The method includes manufacturing a master bulk pattern of a basic cell array on the semiconductor substrate, and storing, in semi-permanent memory, symbol data and detailed data for standard macro cells and standard expanded macro cells prior to designing a logic system. Each macro cell comprises one or more basic cells and has a basic logic function. Each expanded macro cell comprises plural macro cells and has a more complicated and sophisticated logic function than the macro cells. In addition, the logic functions of the expanded macro cells are standard in the logic system design technology area. When a designer creates a logic system, only symbol data for the macro cells and the expanded macro cells, and the connections thereof are used and stored in the memory, so that it is relatively easy to design the system.
    Type: Grant
    Filed: March 22, 1983
    Date of Patent: April 22, 1986
    Assignees: Fujitsu Limited, Fujitsu Microelectronics Inc.
    Inventors: Samuel Chih, Osam Ohba