Abstract: A semiconductor device includes: a first insulating layer with a flat surface formed over a semiconductor substrate structure in which a plurality of semiconductor elements are formed; column-like conductive plugs formed to penetrate the first insulating layer in the thickness direction; elongated wall-like conductive plugs formed through the first insulating layer in the thickness direction; a second insulating layer with a flat surface formed on the first insulating layer covering the column-like conductive plugs and the wall-like conductive plugs; and first wirings having dual damascene structures. Each of the first wirings has a first portion penetrating the second insulating layer in the thickness direction and connected to at least one of the columnar conductive plugs, and a second portion formed in the second insulating layer to an intermediate depth and apparently intersects at least one of the wall-like conductive plugs when viewed above.

Abstract: A delay time adjusting method adjusts a delay time of an input signal so that a phase of the input signal and a phase of an output signal match each other. The delay time adjusting method comprises the step of delaying the phase of the output signal until a phase difference between the phase of the input signal and the phase of the output signal becomes N periods, where N is an integer other than zero.

Abstract: An operation control circuit carries out a first access operation upon receipt of a first access command during activation of a chip enable signal, and carries out a second access operation accessing a memory core in a shorter time than the first access operation, upon receipt of the next access command during activation of the chip enable signal. For this reason, two types of access operations whose access times differ can be carried out by receiving the same access command at the same access terminal. A dedicated terminal for distinguishing between the two types of operations does not need to be formed in a controller, etc., which accesses a semiconductor memory. Selective use of the first and second access operations improves the operation efficiency of the semiconductor memory. Consequently, the operation efficiency of the semiconductor memory can be improved without increasing the cost of a system incorporating the semiconductor memory.

Abstract: According to an aspect of one embodiment, it is provided that semiconductor memory device determining a data read time required to read data from a memory cell by an operation to read a replica cell to which a replica bit line having a load equivalent to a bit line to be connected to the memory cell and a replica word line are connected, the semiconductor memory device comprising: a write control signal generating unit that includes logic gates coupled in multi stages for receiving an input of a replica word line activating signal generated in response to a driving signal for driving the replica word line, the write control signal generating unit generating a write control signal to determine a data write time required to write data in the memory cell based on the replica word line activating signal.

Abstract: A charge loss restoration method detects a memory cell having a tendency of a charge loss within a memory cell array of an electrically writable and erasable nonvolatile semiconductor memory device, using a charge loss detecting reference cell having a threshold value set between a threshold value of a read reference cell and a threshold value of a write verify reference cell, where the threshold value of the write verify reference cell is higher than the threshold value of the read reference cell, and restores the memory cell having the tendency of the charge loss by making an additional write thereto.

Abstract: This invention provides an interface circuit for detecting that a DQS signal from a DDR SDRAM is at an intermediate potential. An interface circuit is connected to at least a signal line which transmits the DQS signal from the DDR SDRAM and reaches an intermediate potential VM when the signal attains an inactive state. The interface circuit has a comparing portion for comparing the potential of the DQS with a threshold potential VREFH which is a potential that is different from the intermediate potential VM.

Abstract: A video encoder includes a frame synchronizer to temporarily store video data supplied from an exterior in a plurality of memory banks repeatedly selected in a predetermined sequence and to read the video data successively from the plurality of memory banks repeatedly selected in said predetermined sequence, an encode unit to encode the video data read by the frame synchronizer, and a control unit to perform a bank switch process that swaps one memory bank among the plurality of memory banks for another memory bank separate from the plurality of memory banks.

Abstract: The invention provides a task scheduling method which can prevent overflowing of a buffer on a host system or a data encoding/decoding apparatus even when the transfer rate falls in case the compressed data and the non-compressed data are simultaneously transferred between the host system and the data encoding/decoding apparatus. In a task scheduling method, the compressed audio/video data is transferred from the buffer of the host system to an external device with a first transfer priority. The non-compressed audio/video data is transferred from the buffer to the external device with a second transfer priority lower than the first transfer priority.