Abstract: A receiver includes a first matching circuit configured to receive antenna input power through a branch point in accordance with a radio signal received by an antenna and input a portion of the received antenna input power to a first circuit as first input power, the antenna input power being input from the antenna, and an impedance of the first matching circuit decreasing as the antenna input power increases, and a second matching circuit configured to receive the antenna input power through the branch point and input another portion of the received antenna input power to a second circuit as second input power, an impedance of the second matching circuit increasing as the antenna input power increases.

Abstract: A resistive random access memory includes a memory cell including a resistive element having a resistance which varies according to a write operation and stores data according to the resistance of the resistive element, a reference resistive element having a resistance set to a first value, a voltage line set to a first voltage during a first write operation in which the resistance of the resistive element is varied from a second value higher than the first value to the first value, and a voltage control circuit arranged between first ends of the two resistive elements. The voltage control circuit adjusts a value of the first voltage supplied from the voltage line so as to reduce a difference between currents flowing through the two resistive elements during the first write operation, and supply the adjusted first voltage to the first ends of the two resistive elements.

Abstract: A receiver includes a first matching circuit configured to receive antenna input power through a branch point in accordance with a radio signal received by an antenna and input a portion of the received antenna input power to a first circuit as first input power, the antenna input power being input from the antenna, and an impedance of the first matching circuit decreasing as the antenna input power increases, and a second matching circuit configured to receive the antenna input power through the branch point and input another portion of the received antenna input power to a second circuit as second input power, an impedance of the second matching circuit increasing as the antenna input power increases.

Abstract: A resistive random access memory includes a memory cell including a resistive element having a resistance which varies according to a write operation and stores data according to the resistance of the resistive element, a reference resistive element having a resistance set to a first value, a voltage line set to a first voltage during a first write operation in which the resistance of the resistive element is varied from a second value higher than the first value to the first value, and a voltage control circuit arranged between first ends of the two resistive elements. The voltage control circuit adjusts a value of the first voltage supplied from the voltage line so as to reduce a difference between currents flowing through the two resistive elements during the first write operation, and supply the adjusted first voltage to the first ends of the two resistive elements.

Abstract: A first-layer insulating film having a barrier property against a determined element contained in a ferroelectric capacitor as well as an oxygen permeability, a hydrogen permeability, and a water permeability is formed over a surface of the ferroelectric capacitor formed over a substrate. After that, heat treatment is performed in an oxidizing atmosphere. After the heat treatment, a second insulating film having a hydrogen permeability and a water permeability lower than those of the first-layer insulating film respectively is formed over a surface of the first-layer insulating film in a non-reducing atmosphere. A third-layer insulating film is formed over a surface of the second-layer insulating film. By doing so, degradation of a ferroelectric film under and after the formation of a semiconductor device having the ferroelectric capacitor is suppressed and deterioration in the characteristics of the ferroelectric capacitor is suppressed.

Abstract: Each pre-sense amplifier produces, in a read operation, an output potential obtained by resistively dividing a power supply voltage based on a potential of one of two first bit lines or one of a plurality of second bit lines. The two first bit lines are connected to a first memory cell holding data of a first and a second logic values. The second bit lines are individually connected to one of a plurality of second memory cells each holding data of the first or the second logic value. Each twin sense amplifier outputs, in the read operation, data determination results based on two reference potentials and a data potential. The two reference potentials are the output potentials produced based on the potentials of the two first bit lines. The data potential is the output potential produced based on the potential of one of the second bit lines.

Abstract: A first pre-sense amplifier connected to reference cells that hold data of logical value “1” via a first bit line outputs a signal that is obtained by delaying a first amplified signal that is obtained by amplifying a voltage of the first bit line when a memory cell is read. A second pre-sense amplifier connected to memory cells via a second bit line generates a second amplified signal by amplifying a voltage of the second bit line when a memory cell is read. The second pre-sense amplifier receives a signal. When a voltage of the signal reaches a threshold or more, the second pre-sense amplifier drops the voltage of the second bit line to a ground potential.

Abstract: Each pre-sense amplifier produces, in a read operation, an output potential obtained by resistively dividing a power supply voltage based on a potential of one of two first bit lines or one of a plurality of second bit lines. The two first bit lines are connected to a first memory cell holding data of a first and a second logic values. The second bit lines are individually connected to one of a plurality of second memory cells each holding data of the first or the second logic value. Each twin sense amplifier outputs, in the read operation, data determination results based on two reference potentials and a data potential. The two reference potentials are the output potentials produced based on the potentials of the two first bit lines. The data potential is the output potential produced based on the potential of one of the second bit lines.

Abstract: A semiconductor device includes a substrate; a transistor formed on a surface of the substrate; a first insulating film formed above the transistor; a second semiconductor film formed on the first semiconductor film; a third semiconductor film formed on the second semiconductor film; a fourth semiconductor film formed on the third semiconductor film; and a ferroelectric capacitor formed on the fourth insulating film, wherein a hydrogen permeability of the third insulating film is higher than a hydrogen permeability of the first insulating film, and a hydrogen permeability and an oxygen permeability of the second insulating film and of the fourth insulating film are higher than the hydrogen permeability and an oxygen permeability of the first insulating film and of the third insulating film.