Abstract: A high-performance, high-reliable backplane bus has a simple configuration and operation. An error reporting network (ERN) provides an inexpensive approach to collecting the error state of a whole system in a uniform and consistent way. The uniformity allows for simpler interface software and for standardized hardware handling of classes of errors. In a preferred embodiment, serial error registers are used, minimizing implementation cost and making the software interface to the serial registers much easier. Serial error information is transferred over a separate data path from the main parallel bus, decreasing the chance of the original error corrupting the error information. Each CPU is provided with a local copy of the entire body of error information. The redundancy minimizes the impact of a possible CPU failure and allows the CPUs to coordinate error recovery.
Type:
Grant
Filed:
June 26, 2003
Date of Patent:
July 29, 2008
Assignee:
Fujitsu Siemens Computers, LLC
Inventors:
Charles Sealey, John Lynch, Mark Myers, Jason Lewis, Stacey Lloyd, Paul Kayfes
Abstract: An interface circuit for interfacing one or more compute nodes to a mesh and for serving a wide range of MPP systems and a method for exchanging data between a first agent on an expansion bus and a second agent on a system bus through a bus bridge so as to maintain cache coherency with data cached by one or more agents on the system bus. Transaction requests are queued within the bus bridge, transactions are snooped on the system bus, and a record of pending transaction addresses is maintained. Issuance of a queued transaction having the same cache line address as a pending transaction is stalled until the pending transaction has been completed.
Abstract: In a massively parallel processing (MPP) system, bandwidth efficiency and message packet latency rates are improved by providing routing elements that detect, isolate and identify various routing errors. More specifically, system lock-up, caused by corrupted message packets, can be prevented by analyzing a given sequence of message packet codes and words as they are received by an input buffer associated with a routing element. By analyzing the sequence, it is possible to determine whether a tail code fails to arrive in the prescribed sequence. If a tail code has been received in a way that is inconsistent with an expected sequence, all of the message packet codes and words received at the buffer can be discarded until a valid message packet start code is received.
Type:
Grant
Filed:
June 24, 1998
Date of Patent:
June 18, 2002
Assignee:
Fujitsu Siemens Computers LLC
Inventors:
Marc Alan Quattromani, Jeffery L. Moll, Mark S. Myers