Abstract: A semiconductor memory includes a power down pulse generating circuit having an output delay time which is dependent on the type of change or transition in an input signal. The pulse generating circuit generates a power down signal at different times depending on whether the input signal changes from a first level to a second level or from the second level to the first level to prevent the power down signal from being output twice when an input clock signal has a pulse width shorter than a normal pulse width thereof. The power down pulse generating circuit generates the power down signal in response to a signal from address transition detection circuitry, and causes data read/write circuitry and bit line pulse generating circuitry to become inactive to reduce power consumption. The bit line pulse generating circuitry generates reset signals which may be used to reset or precharge the bit lines at different timings to reduce peak current in the semiconductor memory.

Abstract: Micro-structures comprising at least a structural member, which is liable to be bent under an external force and formed so as to leave a space between the member and another member liable to be bent and/or other rigid component, are successfully treated using a treating liquid, without suffering permanent deformation resulting from the use of the treating liquid, by removing the micro-structures from the liquid to an environment having a pressure less than the atmospheric pressure; or displacing the micro-structures from the treating liquid to another treating liquid having a smaller surface tension than that of the former liquid, and then removing the micro-structures from the latter liquid; or drying the micro-structures removed from the treating liquid by exposing the same to vapor of a liquid having a smaller surface tension than that of the treating liquid; or removing the micro-structures from the treating liquid to the atmosphere, and drying them using an energy beam of high intensity or an ultrasonic

Abstract: According to the present invention, using a computer aided design system for designing semiconductor integrated circuits wherein a plurality of logic cells forming a circuit net are disposed on a semiconductor chip according to a net list specifying a connection pattern assigned among input and output terminals of a plurality of logic cells and a wiring length connecting the terminals.

Abstract: A CAD system designs mask patterns for use in a master slice integrated circuit processing. The system includes an input device such as a mouse interface, and a display unit for symbolically displaying circuit elements and cells. A first data base stores a net list of circuit design information. A second data base stores data relating to the structure of a master slice bulk and various types of elemental cells formed in the master slice. A processing unit of the CAD system causes the display unit to display both a circuit design scheme and the master slice bulk on a screen of the display unit. The processing unit produces data about the initial positions of a pair of contact hole patterns by which a resistor is defined in a resistive cell region of the master slice, and automatically shifts the contact hole patterns from the initial positions to another position, in order to avoid interference between a wiring pattern on the master slice bulk and the contact hole patterns.