Patents Assigned to Fujitsu
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Patent number: 10078467Abstract: A group generation unit 111 regards, as an invalid area, an area of a first storage medium in which data to be updated is stored and stores updated data in the first storage medium. A reorganization processing unit executes a process of selecting some first groups, calculating, for each of the selected first groups, the number of second storage media to be secured to store data that is stored in an area other than the invalid area of the first storage medium, securing the second storage media according to the levels of priority that are determined according to the calculated number, and transferring the data that is stored in the area other than the invalid area of the first storage medium to the second storage media. A volume management unit moves, to a second group, the first medium on which the transfer performed by the reorganization processing unit completes.Type: GrantFiled: August 4, 2016Date of Patent: September 18, 2018Assignee: FUJITSU LIMITEDInventor: Kenji Uchiyama
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Patent number: 10079258Abstract: An optical detector includes a sensor device chip including a substrate and a sensor device that is provided at a front face side of the substrate and detects light entering from a back face side of the substrate. The sensor device chip has, at the back face side of the substrate, a region in which a refractive index varies so as to increase from a light incident face toward a thicknesswise direction.Type: GrantFiled: November 29, 2017Date of Patent: September 18, 2018Assignee: FUJITSU LIMITEDInventor: Makoto Nakamura
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Patent number: 10078446Abstract: A processor of a parallel computing apparatus accumulates first release requests that are outputted, each of which requests releasing of a storage region that stores management information of a buffer storing data subjected to inter-process communication. Each of the first release requests includes one identifier of the storage region to be released. When the number of accumulated first release requests has reached a threshold, the processor selects first release requests, that request releasing of storage regions of management information that is not presently being used, out of the accumulated first release requests starting from a first release request with an oldest output time as first release requests to be executed. The processor then outputs a single second release request that collectively requests releasing of storage regions of management information indicated in the first release requests to be executed.Type: GrantFiled: September 28, 2015Date of Patent: September 18, 2018Assignee: FUJITSU LIMITEDInventor: Nobutaka Ihara
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Patent number: 10078383Abstract: An apparatus causes a server to execute an application program, and stores, in time series, position-information, obtained by an operation to an input device of the apparatus, on a figure representing a target of the operation on a screen shared between the server and the apparatus. Upon determining that the figure is moved by the operation in the same direction at a speed exceeding a threshold, the apparatus calculates, based on the position-information, first position-information indicating a position at which the figure is expected to be after a lapse of a first time from a current-time where the first time includes a time taken for communication between the apparatus and the server, and transmits the first position-information to the server. Upon receiving, from the server, information of an image on the screen which is obtained by executing the application program based on the first position-information, the apparatus displays the image.Type: GrantFiled: October 4, 2016Date of Patent: September 18, 2018Assignee: FUJITSU LIMITEDInventor: Akira Katsumata
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Patent number: 10079805Abstract: Methods and systems for managing authorized data flows using software defined networking include receiving flow criteria sent from a firewall and extracted from a first data packet, determining whether flow criteria of the first data packet matches an entry in a master data flow list, inserting the flow criteria from the first data packet into the master data flow list on a software defined networking controller, and sending the flow criteria of the first data packet to the router. The router may forward a second data packet associated with the data flow toward a destination based on the validation of the first data packet by the firewall. The flow criteria may not match an entry in a router data flow list on the router and may include at least two of: a source IP address, a destination IP address, a destination port, and a protocol of transmission.Type: GrantFiled: June 13, 2016Date of Patent: September 18, 2018Assignee: FUJITSU LIMITEDInventors: David D. Jameson, Russell DeMolay
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Patent number: 10080308Abstract: An immersion cooling apparatus includes: a refrigerant tank configured to store a non-boiling fluorine-based insulating refrigerant in which an electronic device is to be immersed; a circulation passage of the fluorine-based insulating refrigerant that is located between the refrigerant tank and a refrigerant cooling device; and a sealed pump that is arranged in the circulation passage, is configured to seal a rotor shaft with an impeller and a bearing portion for the rotor shaft in a sealed case while the rotor shaft and the bearing portion are immersed in the fluorine-based insulating refrigerant, and is configured to circulate the fluorine-based insulating refrigerant between the refrigerant tank and the refrigerant cooling device.Type: GrantFiled: March 28, 2017Date of Patent: September 18, 2018Assignee: FUJITSU LIMITEDInventors: Keita Hirai, Hideo Kubo, Naofumi Kosugi
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Patent number: 10078502Abstract: A method may include receiving a model of a graphical user interface (GUI) based application that includes a plurality of paths. The method may further include determining one or more paths of the plurality of paths that each include a pattern that satisfies a rule-pattern. The rule-pattern may be based on potential inaccuracies in the model as indicated by the pattern. The method may additionally include verifying whether the model is consistent with the GUI-based application. The verification may be based on a prioritization of a determination of whether the one or more paths are consistent with the GUI-based application. The prioritization of the one or more paths may be based on the one or more paths each including the pattern.Type: GrantFiled: June 19, 2014Date of Patent: September 18, 2018Assignee: FUJITSU LIMITEDInventors: Mukul R. Prasad, Frolin S. Ocariza, Jr.
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Patent number: 10079209Abstract: A method of manufacturing a graphene film manufactures a graphene film in good state without generating wrinkles and stresses and leaving residues of the resin. The method of manufacturing a graphene film comprises forming a catalyst metal film on a substrate; synthesizing a graphene film on the catalyst metal film; and removing the metal catalyst film in an oxidation atmosphere of an oxidizer and transferring the graphene film to the substrate.Type: GrantFiled: February 25, 2015Date of Patent: September 18, 2018Assignee: FUJITSU LIMITEDInventors: Daiyu Kondo, Haruhisa Nakano
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Patent number: 10078189Abstract: An optical module includes a lens sheet having one or more lenses, a substrate having a photoelectric conversion device mounted on a first face thereof and having a first penetrating hole formed therethrough between the photoelectric conversion device and the one or more lenses, and an adhesive layer configured to bond a face of the lens sheet to a second face of the substrate, wherein the adhesive layer has a second penetrating hole formed therethrough between the one or more lenses and the photoelectric conversion device, and a pathway is provided to connect a space constituted by the first penetrating hole and the second penetrating hole to an outside of the space.Type: GrantFiled: June 28, 2017Date of Patent: September 18, 2018Assignees: FUJITSU COMPONENT LIMITED, FUJITSU LIMITEDInventors: Takuya Uchiyama, Shinichiro Akieda, Mariko Kase
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Patent number: 10079967Abstract: An upper flexible board mounts a circuit. A lower flexible board is in a plate shape larger than a circuit mounting unit, is connected to the upper flexible board by a connecting part, is bent so that the connecting part faces a face opposite to a mounting face of the circuit of the upper flexible board, and includes an area from a bend that is generated by bending an area that does not overlap with the upper flexible board including a second end different from the connecting part to the second end. An iris illuminating LED is disposed on the same side as the upper flexible board in the area. An iris photographing camera is disposed at a position separated from the iris illuminating LED by a certain distance or more and acquires an image of an iris that has received light emission from the iris illuminating LED.Type: GrantFiled: January 6, 2016Date of Patent: September 18, 2018Assignee: FUJITSU LIMITEDInventors: Kenshi Takamoto, Yuji Takemoto, Masaya Yasue
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Patent number: 10079452Abstract: A removal unit includes a latch and a tab separably connectable to the latch. The latch includes latch arms each including a connection hole and an opening extending from the connection hole and being smaller than the connection hole. The tab includes a body, tab arms extending from the body, and protrusions provided on the tab arms to protrude toward each other. The protrusions each include a connecting part and an engaging part extending from the connecting part and being larger than the connection hole. The connecting part is provided on the tab arm, and configured to be placed into the connection hole. The connecting part has a width in a first direction smaller than the width of the opening and a length in a second direction perpendicular to the first direction smaller than the diameter of the connection hole and greater than the width of the opening.Type: GrantFiled: March 7, 2018Date of Patent: September 18, 2018Assignee: FUJITSU COMPONENT LIMITEDInventors: Hongfei Zhang, Shinichiro Akieda
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Patent number: 10079297Abstract: A compound semiconductor device includes a compound semiconductor layer, a gate electrode disposed above the compound semiconductor layer, and source and drain electrodes disposed above the compound semiconductor layer with the gate electrode between the source and drain electrodes, wherein the compound semiconductor layer has a groove in a surface thereof at least between the source electrode and the gate electrode in a region between the source electrode and the drain electrode, the groove gradually deepened toward the source electrode.Type: GrantFiled: March 8, 2017Date of Patent: September 18, 2018Assignee: FUJITSU LIMITEDInventor: Akira Endoh
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Patent number: 10080251Abstract: A wireless communication system includes: a plurality of terminal devices respectively configured to support D2D (Device to Device) communication; and a base station configured to control the plurality of terminal devices. A first terminal device that communicates with a second terminal device via a first D2D link receives identification information of a third terminal device from the third terminal device that communicates with a fourth terminal device via a second D2D link. The first terminal device transmits the identification information of the third terminal device received from the third terminal device to the base station. The base station controls at least one of a resource for the first D2D link and a resource for the second D2D link in such a way that the resource for the first D2D link and the resource for the second D2D link are different from each other.Type: GrantFiled: December 20, 2016Date of Patent: September 18, 2018Assignee: FUJITSU LIMITEDInventor: Hongyang Chen
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Patent number: 10078602Abstract: An information processing apparatus includes: a memory device configured to store data; an arithmetic processor configured to issue a request to be transmitted to the memory device; and a memory controller including: a buffer configured to store one or more unselected requests that are issued by the arithmetic processing processor and are not selected; a history register configured to hold one or more addresses for one or more transmitted requests that have been transmitted to the memory device; and a selection unit configured to select, from the one or more unselected requests stored in the buffer, a target request to be transmitted to the memory device based on the one or more addresses stored in the history register and transmit the target request to the memory device.Type: GrantFiled: April 11, 2016Date of Patent: September 18, 2018Assignee: FUJITSU LIMITEDInventors: Akio Tokoyoda, Masatoshi Aihara, Koichiro Takayama, Koji Hosoe
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Patent number: 10078914Abstract: A setting method executed by a computer includes acquiring display data to be associated with a reference object detected from a first input image data and to be displayed when the reference object is detected from another input image, generating, by the computer, attitude information indicating an arrangement attitude of the display data relative to the reference object, based on rotation information indicating a magnitude of rotation that is applied to the computer by a user, and storing, in a storage device, setting information including the attitude information, the display data, and identification information of the reference object.Type: GrantFiled: August 4, 2014Date of Patent: September 18, 2018Assignee: FUJITSU LIMITEDInventor: Susumu Koga
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Publication number: 20180259633Abstract: A distance measuring device includes one or more processors configured to: detect a wave formed by synthesizing a frequency-swept electromagnetic wave transmitted to an object with a wave reflected on the object; measure, based on the synthesized wave, a distance to the object; calculate a displacement-caused inclination, caused by the displacement of the object, of a power spectrum of the synthesized wave; and measure the distance based on a signal in which the displacement-caused inclination has been removed from the power spectrum.Type: ApplicationFiled: March 7, 2018Publication date: September 13, 2018Applicant: FUJITSU LIMITEDInventors: Yoshio Kikuchi, Osamu Tsuboi
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Publication number: 20180260389Abstract: A method may include identifying an electronic document that includes one or more elements. The method may further include generating a relationship model to provide a probability of assigning relationship between the elements of the electronic document. The method may also include identifying metadata associated with the electronic document. The method may include modifying the relationship model based on the identified metadata. The method may further include segmenting the electronic document into at least two segments based on the modified relationship model. The method may also include extracting information by using natural language processing on the electronic document in view of the at least two segments.Type: ApplicationFiled: March 8, 2017Publication date: September 13, 2018Applicant: FUJITSU LIMITEDInventors: Mehdi BAHRAMI, Wei-Peng CHEN, Takuki KAMIYA
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Publication number: 20180262871Abstract: A location presentation method includes calculating, by a processor, a time lag between time corresponding to a next agenda in an itinerary stored in a storage and calculation start time, extracting, by a processor, a first location to which it is possible to move for visiting from a current place within the time lag and from which it is possible to move to a second location corresponding to the next agenda; and outputting the first location.Type: ApplicationFiled: February 22, 2018Publication date: September 13, 2018Applicant: FUJITSU LIMITEDInventor: Nobumi Noro
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Publication number: 20180260223Abstract: A processing circuit is configured to receive a first binary number composed of a plurality of bits and a second binary number composed of a plurality of bits, and with a digit of the most significant 1-valued bit in the first binary number composed of the plural bits being defined as a first bit digit and with a digit of a bit having a value of 1 first in a higher-order direction than the first bit digit in the second binary number composed of the plural bits being defined as a second bit digit, output a third binary number composed of a plurality of bits out of which a bit corresponding to the second bit digit has a value of 1 and other bits have values of 0, the processing circuit including: a high-order mask processing unit; a low-order mask processing unit; and an output synthesizing unit.Type: ApplicationFiled: February 16, 2018Publication date: September 13, 2018Applicant: FUJITSU LIMITEDInventor: Kensuke Shinomiya
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Publication number: 20180256047Abstract: An information processing apparatus including a processor configured to execute a process including obtaining pieces of waveform data corresponding to a plurality of parts of a subject, the pieces of waveform data indicating a pulse wave of the subject, calculating a first index value indicating a matching degree between the pieces of waveform data, calculating a second index value indicating a matching degree between a plurality of partial waveform data for each of the pieces of waveform data, the plurality of partial waveforms data being generated by dividing each of the pieces of waveform data at predetermined time intervals, determining whether the pieces of waveform data indicates an arrhythmia based on the first index value and the second index value, and outputting information indicating a result of the determining.Type: ApplicationFiled: May 15, 2018Publication date: September 13, 2018Applicant: FUJITSU LIMITEDInventors: Tatsuya Mori, Daisuke Uchida, Kazuho Maeda, Akihiro lnomata