Patents Assigned to Fujitsu
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Publication number: 20180004268Abstract: An information processing system includes: a plurality of devices, each of the devices mounted on a rack and coupled to any one of a plurality of power outlets; and a management apparatus, wherein the management apparatus includes a processor configured to execute power control processing that includes stopping power supply to a first power outlet among the plurality of power outlets, execute determination processing that includes determining whether or not each of the plurality of devices transmits a response to a first packet from the management apparatus to the devices during the power supply to the first power outlet is stopped, and execute recording processing that includes recording identification information of a device from which a response to the first packet is not received, in association with identification information of the first power outlet.Type: ApplicationFiled: June 22, 2017Publication date: January 4, 2018Applicant: FUJITSU LIMITEDInventor: Yuika NARITA
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Publication number: 20180005510Abstract: A situation identification method includes acquiring a plurality of images; identifying, for each of the plurality of images, a first area including a bed area where a place to sleep appears in an image, and a second area where an area in a predetermined range around the place to sleep appears in the image; detecting a state of a subject to be monitored for each of the plurality of images based on a result of detection of a head area indicating an area of a head of the subject in the first area and a result of detection of a living object in the second area; when the state of the subject changes from a first state to a second state, identifying a situation of the subject based on a combination of the first state and the second state; and outputting information that indicates the identified situation.Type: ApplicationFiled: May 30, 2017Publication date: January 4, 2018Applicant: FUJITSU LIMITEDInventors: YASUTAKA OKADA, Kimitaka MURASHITA
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Publication number: 20180004621Abstract: An information processing apparatus obtains start time information indicating a plurality of start times that are calculated when a target program is executed. The target program includes a loop that repeats a process using a plurality of functions. The information processing apparatus obtains a plurality of sampling logs that are generated by intermittent sampling. The information processing apparatus converts each sampling time into a time difference from the immediately preceding start time. The information processing apparatus classifies the plurality of sampling logs into a plurality of time difference segments, and counts, for each of the time difference segments, the number of times execution of each of the plurality of functions is detected. The information processing apparatus displays time-series information indicating a corresponding relationship between the plurality of time difference segments and the functions that are executed, based on the counted number of times.Type: ApplicationFiled: May 30, 2017Publication date: January 4, 2018Applicant: FUJITSU LIMITEDInventor: Masahiro Miwa
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Publication number: 20180006697Abstract: A beam information acquisition method and apparatus and a communications system. The method includes: transmitting a first reference signal to a user equipment by using K antenna elements; receiving a beam index fed back by the user equipment; determining a vector having a length K according to the beam index; estimating a vector having a length L according to the vector having a length K; determining multiple weighting vectors based on the vector having a length L; transmitting the weighted second reference signal to the user equipment; and receiving feedback information on multiple transmission antenna ports fed back by the user equipment, and obtaining beam weighting information according to the feedback information.Type: ApplicationFiled: September 13, 2017Publication date: January 4, 2018Applicant: FUJITSU LIMITEDInventors: Lei SONG, XIN WANG
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Publication number: 20180004618Abstract: A processing method executed by a processor included in a first communication device, the method includes outputting, from a first communication interface of the first communication device, a plurality of data items to a communication path between the first communication interface and a second communication interface of the second communication device while changing a communication setting value regarding the first communication interface; acquiring error information related to the outputting; storing the acquired error information as error management information acquired by associating the communication setting value with the error information; specifying a predetermined number of continuous communication setting values at which an error is not detected based on the error management information; setting a target setting value of the specified communication setting values for the first communication interface; and executing a communication process between the first communication interface for which the targetType: ApplicationFiled: June 15, 2017Publication date: January 4, 2018Applicant: FUJITSU LIMITEDInventor: Yuki HIRANO
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Publication number: 20180004490Abstract: An editing support method executed by a computer, the editing support method including obtaining, from a specified command statement included in a first source code, information designating a second source code and a first replacement rule by which a text included in the second source code is replaced, specifying a storage location of the second source code, obtaining the second source code based on the storage location, generating a third source code by substituting the text included in the second source code in accordance with the first replacement rule, when editing to the third source code is accepted, generating a fourth source code by substituting a text included in the third source code in accordance with a second replacement rule, the second replacement rule indicating a replacement opposite to the first replacement rule, and updating the second source code stored in the specified storage location to the fourth source code.Type: ApplicationFiled: June 27, 2017Publication date: January 4, 2018Applicant: FUJITSU LIMITEDInventor: Masahiro Ichikawa
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Publication number: 20180006721Abstract: An optical transmission module includes: a bias current drive circuit to drive a bias current of a light-emitting element, on a basis of an input bias current setting value; a modulation current drive circuit to drive a modulation current of the light-emitting element, on a basis of an input modulation current setting value; a light-receiving element to measure an optical output power of the light-emitting element; a determiner to determine whether a difference between a target value of the optical output power and the optical output power measured by the light-receiving element is equal to or more than a threshold; and a controller configured to perform a correction control to the bias current drive circuit so that the bias current is reduced in accordance with the difference, when it is determined that the difference is equal to or more than the threshold by the determiner.Type: ApplicationFiled: May 23, 2017Publication date: January 4, 2018Applicant: Fujitsu Optical Components LimitedInventor: Tetsuo Ishizaka
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Publication number: 20180006937Abstract: A method of forwarding information in an information centric networking (ICN) network may be provided. A method may include determining a hit rate for each detected network device of one or more detected network devices. The method may further include selecting at least one network device of the one or more detected network devices having a greatest hit rate. Further, the method may include sending an interest packet to the at least one selected network device.Type: ApplicationFiled: June 30, 2016Publication date: January 4, 2018Applicant: FUJITSU LIMITEDInventors: Lei LIU, Akira ITO
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Publication number: 20180004515Abstract: A processor includes: an address generating unit that, when an instruction decoded by a decoding unit is an instruction to execute arithmetic processing on a plurality of operand sets each including a plurality of operands that are objects of the arithmetic processing, in parallel a plurality of times, generates an address set corresponding to each of the operand sets of the arithmetic processing for each time, based on a certain address displacement with respect to the plurality of operands included in each of the operand sets; a plurality of instruction queues that hold the generated address sets corresponding to the respective operand sets, in correspondence to respective processing units; and a plurality of processing units that perform the arithmetic processing in parallel on the operand sets obtained based on the respective address sets outputted by the plurality of instruction queues.Type: ApplicationFiled: May 26, 2017Publication date: January 4, 2018Applicant: FUJITSU LIMITEDInventors: Shuji Yamamura, Takumi Maruyama, Masato Nakagawa, Masahiro Kuramoto
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Publication number: 20180007755Abstract: A light-source driving apparatus according to an embodiment includes a power supplying unit, a drive unit, and a controller. The power supplying unit generates a voltage by a step-up operation or a step-down operation to output the voltage to one or more light sources. The drive unit drives the one or more light sources. The controller causes the drive unit to drive the one or more light sources after a set time is elapsed from a start of the operation of the power supplying unit. The controller includes a change unit that changes a length of the set time and/or a rise rate of the voltage during the set time on the basis of states of one or more factors that affect a drop in the voltage.Type: ApplicationFiled: May 23, 2017Publication date: January 4, 2018Applicant: FUJITSU TEN LIMITEDInventor: Kazuaki MUROTA
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Publication number: 20180004441Abstract: An information processing apparatus includes a memory and a first processor and a second processor coupled to the memory. The first processor is configured to manage files in a storage apparatus and accesses to the files; and determine a migration target file from the files based on a history of the accesses to the files, the migration target file being to be migrated from a second storage medium to a first storage medium in the storage apparatus, the first and second storage mediums having different performances. The second processor is configured to control migrations of the files between the first storage medium and the second storage medium; and migrate the migration target file from the second storage medium to the first storage medium.Type: ApplicationFiled: April 25, 2017Publication date: January 4, 2018Applicant: FUJITSU LIMITEDInventors: Tatsushi TAKAMURA, Tsuyoshi HASHIMOTO
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Publication number: 20180007530Abstract: A data transfer method includes: executing a process that stores sensor information including duplicate degrees and position information, the duplicate degrees indicating an amount of computers as transmission sources of inhibit signals received by the first computer; executing a process that transmits the inhibit signal including the duplicate degree in the sensor information to a computer that is present in a position to which direct communication via the short-distance radio communication is possible; executing a process that stores the duplicate degree in the inhibit signal, associates the duplicate degree with the transmission source of the inhibit signal, and increases the duplicate degree in the sensor information; and executing a process that transmits the position information in the sensor information to the management device in a case where the duplicate degree in the sensor information is higher than the duplicate degree associated with the transmission source of the inhibit signal.Type: ApplicationFiled: June 9, 2017Publication date: January 4, 2018Applicant: FUJITSU LIMITEDInventors: MIHO TANAKA, Masataka Sonoda, Shunsuke KIKUCHI, Noriyuki FUKUYAMA, Hitoshi UENO
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Publication number: 20180007808Abstract: An information processing apparatus includes an applier that applies an alternating voltage to a lead provided for a frame of a rack that stores one or more electronic devices along a direction of arrangement of the electronic devices, the lead being in contact with a fixing part when the electronic devices are installed; a measure that measures an alternating wave of the alternating voltage flowing through the lead; and a specifier that specifies an installing position of an electronic device by referring to reference waveform information with a waveform of the measure alternating wave, the reference waveform information associating an installing state of the electronic device in the rack with a waveform pattern of the alternating wave measured under the installing state. This configuration reduces steps needed for managing a token, an archive, a token password and enhances the security level of the terminal device.Type: ApplicationFiled: May 26, 2017Publication date: January 4, 2018Applicant: FUJITSU LIMITEDInventor: Yoshinobu MIZUTANI
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Publication number: 20180005687Abstract: A semiconductor device includes an oscillator that oscillates to generate a clock, a circuit that operates based on the clock generated by the oscillator, a temperature detector that detects the temperature of the circuit, a power detector that acquires, as a monitored power value, power consumed by the circuit, and a frequency controller that controls, when the temperature detected by the temperature detector exceeds a temperature threshold, the frequency of the clock of the oscillator so that the monitored power value matches target power that causes the temperature of the circuit to converge to a temperature higher than the temperature threshold.Type: ApplicationFiled: June 23, 2017Publication date: January 4, 2018Applicant: FUJITSU LIMITEDInventor: Yukihito KAWABE
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Publication number: 20180006563Abstract: A regulator circuit includes a first transistor reducing an external supply voltage and outputting an internal active voltage to an output node; a first detector receiving a criteria level, detecting the internal active voltage based on an enable signal, controlling a gate voltage of the first transistor, and adjusting an output current thereof; a second transistor reducing the external supply voltage, and outputting an internal standby voltage corresponding to the internal active voltage to the output node; a second detector receiving a reference voltage, detecting the internal standby voltage regardless of the enable signal, controlling a gate voltage of the second transistor, and adjusting an output current thereof; a first switch controlling whether to output the reference voltage as the criteria level of the first detector; and a second switch controlling whether to output the voltage of the output node as the criteria level of the first detector.Type: ApplicationFiled: May 31, 2017Publication date: January 4, 2018Applicant: FUJITSU SEMICONDUCTOR LIMITEDInventor: Atsushi Nakakubo
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Publication number: 20180006756Abstract: An optical receiver includes a demultiplexer configured to demultiplex, for each channel, optical signals input through a plurality of channels, a photoelectric converter having a number of light receivers corresponding to the plurality of channels, the photoelectric converter being configured to convert an optical signal into an electric signal for each channel, a monitor circuit configured to monitor, for each channel, an amplitude characteristic of the optical signal converted into the electric signal by the photoelectric converter, and a control circuit configured to control, based on a monitored result of the monitor circuit, a bias voltage to be applied to the light receiver such that an amount of variability in the amplitude characteristic between the channels is minimum or falls within a predetermined range.Type: ApplicationFiled: June 28, 2017Publication date: January 4, 2018Applicant: Fujitsu Optical Components LimitedInventor: Toshio ISHII
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Publication number: 20180004626Abstract: A non-transitory computer-readable storage medium storing an evaluation program that causes a computer to execute a process, the process including receiving designation of a software, obtaining an execution condition used for an execution request for the designated software based on information stored in a memory, the execution request having been issued by the specified software, the information associating the designated software with the execution condition, executing the execution request for the designated software, by using the acquired execution condition, acquiring log information regarding an execution of the designated software when the designated software is executed in response to the execution request, performing an evaluation related to the specified software, based on the acquired log information, and outputting an evaluation result.Type: ApplicationFiled: June 28, 2017Publication date: January 4, 2018Applicant: FUJITSU LIMITEDInventors: Naohiro Kishishita, Makoto Adachi, Hiroshi Iyobe, Yosuke Naka, Takaaki Nakazawa, Takeya Mutoh, Shunichi Obinata, Kazuki Yamada
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Publication number: 20180006879Abstract: A gateway apparatus including a first inter-device interface configured to communicate with a monitoring apparatus; a second inter-device interface configured to communicate with multiple subordinate base station apparatuses; a memory; and a processor coupled to the memory. The processor is configured to generate first configuration information when second configuration information is received from the monitoring apparatus via the first inter-device interface. The processor generates the first configuration information by performing protocol conversion of converting the second configuration information into a format adapted to the second inter-device interface for the multiple base station apparatuses. The processor is further configured to transmit the generated first configuration information to the multiple base station apparatuses via the second inter-device interface, and divide the multiple base station apparatuses into predetermined groups.Type: ApplicationFiled: September 13, 2017Publication date: January 4, 2018Applicant: FUJITSU LIMITEDInventors: Yuta AOKI, Osamu YAMANO
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Publication number: 20180006175Abstract: A semiconductor bulk structure includes a bulk structure including a portion where two layers of GeSe and one layer of WS2 are alternately laminated. And an optical device includes a semiconductor bulk structure having a bulk structure including a portion where two layers of GeSe and one layer of WS2 are alternately laminated.Type: ApplicationFiled: June 9, 2017Publication date: January 4, 2018Applicant: FUJITSU LIMITEDInventor: Mari Ohfuchi
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Publication number: 20180004635Abstract: A method to discover an input sequence for an unknown binary program is provided. The method may include obtaining a first input sequence for an unknown binary program. The method may also include generating multiple mutated input sequences from the first input sequence and executing the unknown binary program with the first input sequence and/or the mutated input sequences as the input. The method may further include recording one or more branch counts and execution traces of the executions of the unknown binary program and selecting an execution trace that is different or has a different branch count from the other execution traces of the unknown binary program. A branch in the selected execution trace may be negated to generate a symbolic path condition and the symbolic path condition may be solved to discover a second input sequence for the unknown binary program.Type: ApplicationFiled: June 30, 2016Publication date: January 4, 2018Applicant: FUJITSU LIMITEDInventor: Praveen MURTHY