Patents Assigned to Fujitus Limited
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Patent number: 8740454Abstract: An optical fiber is provided with a first measurement portion and a second measurement portion provided with covering layers different at least in any one of heat capacity and heat conductivity. Then, the first measurement portion and the second measurement portion are located in the same measurement position and light is inputted from a temperature measurement device into the optical fiber. Thereafter, the temperature measurement device receives backscattered light generated inside the optical fiber to measure temperature distribution in a longitudinal direction of the optical fiber. An analyzer analyzes a variation over time of the temperature distribution outputted from the temperature measurement device to calculate a temperature and a wind velocity in a measurement position where the first measurement portion and the second measurement portion are located.Type: GrantFiled: August 1, 2012Date of Patent: June 3, 2014Assignee: Fujitus LimitedInventors: Fumio Takei, Kazushi Uno, Takeo Kasajima
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Patent number: 7532595Abstract: A mobile terminal includes a channel estimation processor to obtain the channel estimation value of a first channel reception signal in use of a plurality of known signals received from a base station within a channel estimation period; a channel compensation processor to perform a compensation process of the first channel reception signal in use of the channel estimation value; and a controller to control the channel estimation period so as to use a known signal which is received after the reception of the first channel reception signal for channel compensation. With this, throughput in downlink communication can be improved by controlling the deterioration of HS-SCCH reception quality itself without any particular transmission power control with the base station even under an environment such as high speed fading.Type: GrantFiled: March 20, 2006Date of Patent: May 12, 2009Assignee: Fujitus LimitedInventor: Keiji Nibe
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Publication number: 20060155521Abstract: In a verification supporting apparatus, when an obtaining unit obtains a verification scenario, a substituting unit substitutes an undefined value for a variable value in the verification scenario. A first executing unit executes a logic simulation using an input pattern. From a result of the logic simulation, a determining unit generates code-coverage upper-limit information. A setting unit sets input patterns by giving an arbitrary logic value to the variable value. A second executing unit executes a logic simulation using the input patterns set. A generating unit generates code coverage from the input patterns set. A calculating unit calculates a level of achievement of the code coverage with respect to the code-coverage upper-limit information.Type: ApplicationFiled: April 28, 2005Publication date: July 13, 2006Applicant: FUJITUS LIMITEDInventor: Hiroaki Iwashita
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Patent number: 6157335Abstract: A voltage generating circuit for a digital to analog converter divides a potential difference between a high potential supply and a low potential supply. The voltage generating circuit includes a voltage dividing circuit having three impedance elements connected in series between the high potential supply and the low potential supply. A first current source is connected to a node between the first two series connected impedance elements and a second current source is connected to a node between the second and third series connected impedance elements. The first and second current source supply first and second currents having the same value to the first and second nodes, respectively. A control circuit compares a reference voltage with a selected voltage output from the voltage dividing circuit and controls the first and second currents supplied by the first and second current source so that the selected voltage is made equal to the reference voltage.Type: GrantFiled: July 30, 1998Date of Patent: December 5, 2000Assignee: Fujitus LimitedInventors: Hisao Suzuki, Norikazu Fushimi
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Patent number: 5568479Abstract: The present invention relates to a system for controlling a miscellaneous device such as a remote device associated with an exchange which handles a fixed length cell with a control field and an information field. The object of the invention is to offer a system where an exchange can control a miscellaneous device such as a remote device in accordance with the feature of the exchange. The exchange includes a call processor, a switch and a signal device. In order to control the miscellaneous device, a path is formed between the signal device and the miscellaneous device. Control information from the call processor is cellulated. The path notifies the miscellaneous device of the control information including cell via the switch to control the miscellaneous device by the exchange.Type: GrantFiled: October 10, 1995Date of Patent: October 22, 1996Assignee: Fujitus LimitedInventors: Yoshihiro Watanabe, Satoshi Kakuma, Sumie Morita, Yuzo Okuyama, Kenichi Okabe
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Patent number: 5561662Abstract: A switch interface unit, a monitor unit, and a control system interface unit are connected as external units to a highway to which a subscriber information processing unit is also connected so that a monitoring process, that is, a special study process, can be simplified and a cost charged for the subscriber information processing unit can be prevented from increasing greatly. Furthermore, in an accounting process, accounting parameters are accumulated in an accounting information accumulating unit for variations on compressed source addresses, not on source addresses. As a result, the accounting information accumulating unit, etc. can be realized with normal circuit elements only.Type: GrantFiled: March 17, 1994Date of Patent: October 1, 1996Assignee: Fujitus LimitedInventors: Satoshi Kakuma, Kazuo Hajikano, Masami Murayama, Shuji Yoshimura, Shiro Uriu, Jin Abe
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Patent number: 4803535Abstract: A dynamic random access memory having a trench capacitor includes: a semiconductor substrate; a trench formed in a semiconductor substrate; an insulating layer formed on an inner surface of the trench and having a bottom opening; a first conductive layer formed at the bottom opening position and on the insulating layer and the first conductive layer is ohmically connected to the semiconductor substrate at the bottom opening. The device includes further a dielectric layer formed on the first conductive layer; a second conductive layer formed on the dielectric layer so as to fill the trench, the first conductive layer, the dielectric layer, and the second conductive layer constituting a charge storage capacitor; and a MIS transistor formed in the semiconductor substrate, wherein the second conductive layer is ohmically connected to a source or drain region of the MIS transistor.Type: GrantFiled: March 2, 1987Date of Patent: February 7, 1989Assignee: Fujitus LimitedInventor: Masao Taguchi