Abstract: A digital bus arrangement and an associated method are disclosed. The bus arrangement includes an input synchronization layer and an output synchronization layer. Data transfer between the modules is synchronized using a master clock signal such that data originated by one module is latched and placed on the bus in one clock cycle. Thereafter, in a second or subsequent clock cycle, the data is synchronously latched at the other modules of the system such that the data is available to an intended module. No logic circuitry is present between the input and output synchronization layers.

Abstract: Bus arrangements for interconnecting a number of discrete and/or integrated modules in a digital system are described herein. Implementations of the bus arrangements are contemplated at chip level, forming part of an overall integrated circuit, and are also contemplated as interconnecting discrete modules within an overall processing system. These bus arrangements and associated method provide for high speed, efficient digital data transfer between the modules through optimizing bus utilization by eliminating the need for maintaining a fixed time relationship between the address and data portions of transactions which are executed by the system. In this manner, the bus arrangement is capable of supporting more active transactions than the number of individual buses which make up the bus arrangement. Systems disclosed may include any number of individual buses within their bus arrangements.

Abstract: A method and associated arrangement for use in priority allocation in a bus interconnected digital multi-module system are described. The modules are configured for requesting the use of the bus with each module being granted its request based upon its priority. During the operation of the system, a set of priorities is established such that the number of priorities is equal to the number of modules in the system. Each module may be reassigned to priorities which are different than their initial priorities. In addition, the priorities may be grouped in an initial group arrangement which may be reconfigured. The group arrangement may be reconfigured in any desired manner. Also, provisions are made for refusing a grant to a module even though the module possesses the highest priority among requesting modules.

Abstract: Bus arrangements for interconnecting a number of discrete and/or integrated modules in a digital system are described herein. Implementations of the bus arrangements are contemplated at chip level, forming part of an overall integrated circuit, and are also contemplated as interconnecting discrete modules within an overall processing system. These bus arrangements and associated method provide for high speed, efficient digital data transfer between the modules through optimizing bus utilization by eliminating the need for maintaining a fixed time relationship between the address and data portions of transactions which are executed by the system. In this manner, the bus arrangement is capable of supporting more active transactions than the number of individual buses which make up the bus arrangement. Systems described may include any number of individual buses within their bus arrangements.

Abstract: Bus arrangements for interconnecting a number of discrete and/or integrated modules in a digital system are described herein. Implementations of the bus arrangements are contemplated at chip level, forming part of an overall integrated circuit, and are also contemplated as interconnecting discrete modules within an overall processing system. These bus arrangements and associated method provide for high speed, efficient digital data transfer between the modules through optimizing bus utilization by eliminating the need for maintaining a fixed time relationship between the address and data portions of transactions which are executed by the system. In this manner, the bus arrangement is capable of supporting more active transactions than the number of individual buses which make up the bus arrangement. Systems described may include any number of individual buses within their bus arrangements.