Abstract: A system is provided for transferring 32-bit data words between a 32-bit host personal computer and an IDE peripheral storage device adapted to transfer data as 16-bit words and store the data in a data register identified by an offset address. The system microprocessor transfers 32-bit data words from an internal 32-bit data transfer register in two sequential 16-bit words without an intervening input or output instruction and automatically increments the offset address associated with the second 16-bit word. A device driver program or a peripheral BIOS directs the microprocessor to address data transfers from the 32-bit register to an alias address, the offset address portion of which is incremented for the second 16-bit word. An interface adapter circuit is provided which includes logic circuitry for recognizing an address as an alias, and translating the offset portion of the alias address to offset address associated with the peripheral's data register.

Abstract: A small computer system interface (SCSI) controller circuit, connected between a host computer bus and a SCSI bus, includes a storage buffer shared between command and data signals provided by a host computer to a target SCSI peripheral device. The shared buffer includes a bidirectional FIFO which is used for intermediate storage of command blocks between transferred the host and the target device as well as data blocks. In the case of data transfers from the host to the target device, a command block is written to the bidirectional FIFO followed by as much of the data block as will fit in the remaining FIFO space. After the target device has read the command block, it accesses the SCSI bus and begins the transfer of data from the FIFO. In the case of data transfers from the target device to the host, a data transfer command block is first written to the FIFO by the host. The command block is read by the target device which then provides the requested data to the FIFO over the SCSI bus.

Abstract: A single chip peripheral bus adapter circuit has a pair of input and output first in, first out (FIFO) buffers, a main buffer, and a pair of supporting registers. The registers increase the performance of the circuit by eliminating or reducing wait states.

Abstract: A single chip SCSI controller circuit has a pair of input and output first in, first out (FIFO) buffers as well as a main buffer. The circuit supports synchronous and asynchronous data transfers which are fully compatible with the SCSI-II specification. A mode select pin may be selectively actuated by the user or by attached interface circuitry to configure the chip for either microchannel architecture (MCA) or industry standard architecture (ISA) compatibility.

Abstract: An automatic SCSI termination circuit has means detecting the occupied or vacant status of one or more SCSI interconnection ports and enables or disables termination, which is applied to the ports without need for manual intervention.