Abstract: An image-processing unit for an electronic device is disclosed. The image-processing unit may include a digital signal processor (DSP), a first control interface configured for receiving an AP-instruction from an application processor (AP) external to the image-processing unit, and a second control interface configured for transmitting an intermediary-instruction generated by DSP based on the AP-instruction. The image-processing unit may further include a first data interface configured for receiving sensor-data generated in response to the intermediary-instruction by a sensor external to the image-processing unit, and a second data interface configured for bi-directionally transmitting intermediary-data to the AP or receiving AP-data from the AP, wherein the intermediary-data is generated by the DSP based on the sensor-data.

Abstract: A multi-controller multi-memory device is disclosed. The device may include a plurality of controllers and a plurality memory units (m-units). Each controller is connected with a dedicated request-distribution unit (dist-unit) and a dedicated read-selection unit (read-unit). Each m-unit is connected with a dedicated arbitration unit (abt-unit). A controller's dedicated dist-unit is coupled with each of the abt-units dedicated to the plurality of m-units. The controller is configured to transmit a data-request to the controller's dedicated dist-unit, the data-request addressing an m-unit. The controller's dedicated dist-unit is configured to transmit the data-request to an abt-unit dedicated to the m-unit. The abt-unit is configured to select the data-request for transmitting to the m-unit based on an arbitration process.

Abstract: An image-processing unit for an electronic device is disclosed. The image-processing unit may include a digital signal processor (DSP), a first control interface configured for receiving an AP-instruction from an application processor (AP) external to the image-processing unit, and a second control interface configured for transmitting an intermediary-instruction generated by DSP based on the AP-instruction. The image-processing unit may further include a first data interface configured for receiving sensor-data generated in response to the intermediary-instruction by a sensor external to the image-processing unit, and a second data interface configured for bi-directionally transmitting intermediary-data to the AP or receiving AP-data from the AP, wherein the intermediary-data is generated by the DSP based on the sensor-data.

Abstract: An imaging structure for a portable electronic device is disclosed. The imaging structure may include a housing with an opening for obtaining an external light. The structure may include a reflective module having a first reflective surface and a second reflective surface for reflecting the external light. The reflective module includes a linear movement switching mechanism configured to move the reflective module in a linear direction inside of the housing.

Abstract: A method for storing data related to video decoding is described. A video-decoding device may divide a video image into a plurality of coding units (CUs). Each of the plurality of CUs has a horizontal coordinate and a vertical coordinate. The video-decoding device may retrieve a first tidbit associated with a first CU from a one-dimensional storage structure. The first CU is adjacent to an un-decoded second CU. The first tidbit is generated during decoding of the first CU and stored in the one-dimensional storage structure based on a first storage index calculated using the first CU's horizontal and vertical coordinates. The video-decoding device may further decode the second CU based on the first tidbit, and store a second tidbit associated with the second CU in the one-dimensional storage structure based on a second storage index calculated using the second CU's horizontal and vertical coordinates.

Abstract: An imaging structure for a portable electronic device is disclosed. The imaging structure may include a housing having an opening for obtaining external light. The imaging structure may also include a reflective module coupled with the housing. The reflective module may include a reflective surface for reflecting the external light. The imaging structure may further include a photo-sensing module coupled with the reflective module. The photo-sensing module may be configured to generate an image based on the external light reflected from the reflective module toward the photo-sensing module.

Abstract: An image-processing unit for an electronic device is disclosed. The image-processing unit may include a digital signal processor (DSP), a first control interface configured for receiving an AP-instruction from an application processor (AP) external to the image-processing unit, and a second control interface configured for transmitting an intermediary-instruction generated by DSP based on the AP-instruction. The image-processing unit may further include a first data interface configured for receiving sensor-data generated in response to the intermediary-instruction by a sensor external to the image-processing unit, and a second data interface configured for transmitting to the AP intermediary-data generated by the DSP based on the sensor-data.

Abstract: A multi-controller multi-memory device is disclosed. The device may include a plurality of controllers and a plurality memory units (m-units). Each controller is connected with a dedicated request-distribution unit (dist-unit) and a dedicated read-selection unit (read-unit). Each m-unit is connected with a dedicated arbitration unit (abt-unit). A controller's dedicated dist-unit is coupled with each of the abt-units dedicated to the plurality of m-units. The controller is configured to transmit a data-request to the controller's dedicated dist-unit, the data-request addressing an m-unit. The controller's dedicated dist-unit is configured to transmit the data-request to an abt-unit dedicated to the m-unit. The abt-unit is configured to select the data-request for transmitting to the m-unit based on an arbitration process.

Abstract: A method for storing data related to video decoding is described. A video-decoding device may divide a video image into a plurality of coding units (CUs). Each of the plurality of CUs has a horizontal coordinate and a vertical coordinate. The video-decoding device may retrieve a first tidbit associated with a first CU from a one-dimensional storage structure. The first CU is adjacent to an un-decoded second CU. The first tidbit is generated during decoding of the first CU and stored in the one-dimensional storage structure based on a first storage index calculated using the first CU's horizontal and vertical coordinates. The video-decoding device may further decode the second CU based on the first tidbit, and store a second tidbit associated with the second CU in the one-dimensional storage structure based on a second storage index calculated using the second CU's horizontal and vertical coordinates.

Abstract: An imaging structure for a portable electronic device is disclosed. The imaging structure may include a housing having an opening for obtaining external light. The imaging structure may also include a reflective module coupled with the housing. The reflective module may include a reflective surface for reflecting the external light. The imaging structure may further include a photo-sensing module coupled with the reflective module. The photo-sensing module may be configured to generate an image based on the external light reflected from the reflective module toward the photo-sensing module.

Abstract: The invention discloses a NAND flash controller, including a command and address data transmission channel adapted to connect the bus timing interface with the channel selector and transmit command and address data, a data buffer region adapted to receive message data from the bus timing interface through system bus, a control register adapted to receive an operation parameter configured through system bus via the bus timing interface, a logic controller adapted to write the data information into or read the data information from the data buffer region according to the operation parameter, a channel selector adapted to connect the DMA data transmission channel or the command and address data transmission channel according to the operation parameter for transmitting data. The invention also discloses a date exchange method between NAND flash controller and NAND flash memory. The invention improves the data transmission efficiency and is compatible with various NAND flash memories.

Abstract: The invention discloses a NAND flash controller, including a command and address data transmission channel adapted to connect the bus timing interface with the channel selector and transmit command and address data, a data buffer region adapted to receive message data from the bus timing interface through system bus, a control register adapted to receive an operation parameter configured through system bus via the bus timing interface, a logic controller adapted to write the data information into or read the data information from the data buffer region according to the operation parameter, a channel selector adapted to connect the DMA data transmission channel or the command and address data transmission channel according to the operation parameter for transmitting data. The invention also discloses a date exchange method between NAND flash controller and NAND flash memory. The invention improves the data transmission efficiency and is compatible with various NAND flash memories.