Abstract: A method for migrating a hierarchical layout between manufacturing processes is accomplished without specification of a technology file and design rules. Different scaling factors and bias values in the X and Y directions may be applied to each layer in the source hierarchical layout during the migration. In addition, the target hierarchical layout maintains connectivity, and is free of notches, jogs and small edges. A cell hierarchy tree is created, which guides expansion of the target hierarchical database to resolve issues related to rounding of floating point numbers to integers. Boolean operations are performed to determine the differences between target flat database and the target hierarchical database. The differences are eliminated by modifying the target hierarchical database to match the layout in the flat database.

Abstract: A method for reducing the size of post-layout circuit simulation output waveform database without a loss of essential information and accuracy. The reduced waveform database requires significantly less storage than the typical waveform database for post-layout simulation, thereby improving the time required for a waveform tool to access, and for a user to navigate, the post-layout simulation results. The method therefore greatly improves designer productivity during circuit verification and debugging phases. The method can be carried out in a preprocessor to a circuit simulator, in a post-processor to a circuit simulator, or may be directly built into a circuit simulator. The method is applicable to any post-layout netlists with schematic node names or circuit element names.