Abstract: A RAKE combiner apparatus uses a charge transfer element, which can permit a high-precision RAKE receiver to be constructed by a simple circuit structure, has lower consumption power, can allow the finger number to be arbitrarily set within a range of up to the number of taps of the matched filter and can implement a highly efficient RAKE process.

Abstract: A random pulse type radar apparatus sends out as an output signal a spectrum spread radio wave including a pseudo random signal-less period and receives echoes in this signal-less period to thereby significantly reduce transmission peak power.

Abstract: A general purpose charge mode, analog operation circuit provides adder, multiplier, divider (D/A converter) and other functions using a single hardware configuration to be used in different modes. A two-dimensional lattice circuit including electrical charge transfer devices, each driven by charge transfer electrodes, all or a portion of which having structures allowing independent control, and a plurality of the electrical charge transfer devices adjacent to each other in the circuit are controlled successively with respect to the analog circuit charge signals to provide operation functions such as addition, multiplication, division, and sign inversion.

Abstract: A data supply method for performing exact operations by a number of operation units receiving a single signal as input is proposed; and a composition of a system provided with both the filter function and the AD conversion function using the same is also proposed. The system comprises a charge signal supply unit, which is a charge splitter composed of charge transfer devices for splitting a input charge signal into N signal charge parts, for supplying as input for said charge splitter S (S is an integer equal or superior to 2) series of source time series charge signals as a single time series signal by multiplexing the same by the time division multiplexing; and a demultiplexing mechanism for taking as respective inputs the N outputs from said charge splitter, and for separating multiplexed S series of time series charge signals contained in this input to convert them into an independent time series signals.

Abstract: A charge mode operation circuit dedicated to detect the correlation between analog input signal and digital code, and for realizing by "RAKE method" the path diversity reception from the correlation data obtained using the same. The circuit utilizes an analog shift register using at least one charge transfer device for transferring a charge signal packet, a plurality of charge signal generation units, arranged along the analog shift register and provided, respectively, with substantially uniform voltage charge conversion characteristic controlled by a common input sign; and a routing mechanism for selectively transferring output charge packets generated by the plurality of charge signal generation units in given directions according to digital bit signal provided separately.

Abstract: A charge mode operation circuit dedicated to detect the correlation between analog input signal and digital code, and for realizing by "RAKE method" the path diversity reception from the correlation data obtained using the same. The circuit utilizes an analog shift register using at least one charge transfer device for transferring a charge signal packet, a plurality of charge signal generation units, arranged along the analog shift register and provided, respectively, with substantially uniform voltage charge conversion characteristic controlled by a common input sign; and a routing mechanism for selectively transferring output charge packets generated by the plurality of charge signal generation units in given directions according to digital bit signal provided separately.

Abstract: A multiplier using a charge transfer device, broadly applicable to analog signal processing, digital-to-analog (D/A) conversion, or parallel image processing. The multiplier includes a charge transfer device with at least 8 independent potential wells arranged in a ring, and charge signal accumulators having at least one set of a plurality of independently controlled potential wells connected in serial to at least one of these potential wells on the ring.

Abstract: A systolic array processor is provided which is adapted to virtually constitute a number of analog type pipelining processors which operate in a parallel manner on an analog type shift register array such as a CCD or the like. The processor is composed of a plurality of signal processors for performing signal processings for a plurality of signals including an analog signal or signals supplied as input signals thereto and determining analog outputs, a shift register array or shift register mesh consisting of a plurality of shift registers, and a timing controller for controlling signal processings, arithmetic additions, shift operations and sequences in time of control for shift directions, of the shift registers. The shift register array or mesh includes analog shift registers having functions of performing the addition of input signals, and the analog outputs are supplied to the analog shift registers as one input signals thereof, respectively.

Abstract: Analog memories such as CCD, which are advantageous in less power consumption and higher integration density, are used to configure a system for highly accurately executing digital/analog processing. A digital to analog converter according to the invention has at least one first analog memory having an input port for receiving input signal packets and a partial output drive port for driving the i-th output signal packet; at least one second analog memory having a function to integrate input signal packets applied thereto; and at least one signal packet routing mechanism for selectively routing output signal packets from the first analog memory according to an input digital signal bit. The extremely simple configuration of the present invention may be effectively utilized for realizing an ultra-parallel analog processor as well as applied to other fields such as video processing by combining a function of an input means for optical signals, which has been a main application of the CCD.

Abstract: Analog memories such as CCD, which are advantageous in less power consumption and higher integration density, are used to configure a system for highly accurately executing analog/digital processing. An analog to digital converter according to the invention has at least one first analog memory having an input port for receiving input signal packets and a partial output drive port for driving the i-th output signal packet; at least one second analog memory having a function to integrate input signal packets applied thereto; and at least one signal packet routing mechanism for selectively routing output signal packets from the first analog memory according to an input digital signal bit. The extremely simple configuration of the present invention may be effectively utilized for realizing an ultra-parallel analog processor as well as applied to other fields such as video processing by combining a function of an input means for optical signals, which has been a main application of the CCD.

Abstract: The apparatus includes a plurality of groups of plural data paths which are connected in such a manner that each data path of one group intersects with one or more data paths of another or more data path groups. Each data path of each group is composed of a shift register and at least one of the data paths of each group transfer a signal imputed thereto in a different direction from at least one of the remaining data paths thereof when one of the shift registers thereof is operated.

Abstract: A fuzzy logic operation circuit for two inputs includes two identical charge coupled devices having at least first and second gate electrodes connected in parallel on an output side and floating gates provided to a transfer electrode on an input side. A comparison device compares charge detection signals from the floating gates with each other and selects an input signal of either the smaller or greater of the two inputs by the comparison output.

Abstract: A fuzzy computer includes a defuzzifier composed of charge coupled devices which intake and transfer a set of fuzzy data elements in parallel. Pairs of positive and negative gate electrodes are located transversely to the charge coupled devices. The gate electrodes in each pair differ in their effective area to the corresponding charge coupled devices and all the positive and negative electrodes are connected together in respective groups. Each of the positive and negative groups senses independently as an electronic signal, such as voltage, the sum of weighted charge value at each charge coupled device behind the electrodes, multiplying by the weighing factors which are determined by the effective area of each electrode. A total output is obtained as the difference of the output signals at the positive and negative electrode groups.

Abstract: A fuzzy logic operation circuit for two inputs includes two identical charge coupled devices having at least first and second gate electrodes connected in parallel on an output side and floating gates provided to a transfer electrode on an input side. A comparison device compares charge detection signals from the floating gates with each other and selects an input signal of either the smaller or greater of the two inputs by the comparison output.A fuzzy computer includes a defuzzifier composed of charge coupled devices which intake and transfer a set of fuzzy data elements in parallel. Pairs of positive and negative gate electrodes are located transversely to the charge coupled devices. The gate electrodes in each pair differ in their effective area to the corresponding charge coupled devices and all the positive and negative electrodes are connected together in respective groups.

Abstract: A sequential chirp modulation-type spread spectrum communication system is disclosed relating to the FH-type which realizes fine transmission quality at low cost. It comprises at least primary and secondary digital sine wave generators of a program controlled-type mounted respectively on a transmitter of a transmitting side and a receiver of a receiving side. The primary sine wave generator generates a sine wave having a frequency which changes almost continuously and Pseudo-Random in the specified range of frequency according to the program. The primary digital sine wave generator also transmits the sine wave from the transmitting side after modulating the sine wave with the signals which should be transmitted. The secondary digital sine wave generator generates a sine wave having a frequency in which the specified frequency is a constant distance from the receiving signal frequency and receiving the receiving signal after demodulating.