Abstract: The refresh address generator of a memory includes, in part, a counter, a multitude of shift registers and multiplexers, and a comparator. With each clock cycle, the counter increments and stores the refresh count address, and the addresses stored in the counter and the shift registers prior to the increment operation is shifted out and stored in a pipelined fashion. If the array address stored in the last stage of the register pipeline is equal to the address of the array read out during the cycle immediately preceding the refresh cycle or is equal to the address of the neighboring array of the read out array, the comparator causes multiplexer to select the address stored in the counter as the refresh address. This address differs from the address of the array read out during the immediately preceding cycle by at least two counts.

Abstract: A significantly more efficient implementation of a DLL for systems using two separate clock signals, whereby a single DLL circuit is used to provide for locking of both clock signals. According to the present invention, the input to the DLL is controlled such that it responds to edges of both clock signals. The present invention provides a circuit receiving a first periodic signal CLK1 and a second periodic signal CLK2, there being a phase difference between CLK1 and CLK2, the circuit including a delay-locked loop (DLL) having one delay path, wherein the same delay path provides delay tuning for both CLK1 and CLK2.

Abstract: A circuit according to the present invention includes a plurality of data registers each coupled between the output terminal and a data bus. Each data register stores successive data bits received serially from the data bus. The circuit also includes a plurality of output enable signals each coupled to a corresponding data register. Additionally, the circuit includes a mode select circuit to program the plurality of output enable signals to operate in one of a plurality of modes corresponding to a programmable latency period, wherein in a first mode the output enable signals have a first pulse width and in a second mode the output enable signals have a second pulse width greater than the first pulse width. The circuit may be included as part of a memory circuit in a memory system.

Abstract: A method and apparatus for testing memory devices. One embodiment provides a method including receiving a first input data bit having a first polarity, and receiving a second input data bit having a second polarity, wherein the second polarity is the complement of the first polarity. The method also includes writing the first input data bit to a first portion of a plurality of memory cells, writing the second input data bit to a second portion of a plurality of memory cells, and reading data bits from the first and second portions of the plurality of memory cells. An active signal is generated if the data bits read from the first portion of the plurality of memory cells and complements of the data bits read from the second portion of the plurality of memory cells each have the same polarity.

Abstract: In an embodiment of this invention, a memory includes an array of memory cells, an address decoder configured to generate a decoded signal for selecting a plurality of memory cells in a memory access, an input/output block configured to transfer data corresponding to the selected memory cells into and out of the memory, a first timing circuit configured to generate a first timing signal, and a second timing circuit configured to receive the first timing signal and in response generate a strobe signal coupled to the input/output block. An interconnect line carrying the first timing signal is routed through the array so that in the memory access a time delay from when the decoded signal is generated to when the data arrives at an input terminal of the I/O block is substantially the same as a time delay from when the first timing signal is generated to when the strobe signal is generated. A memory access time is thus improved by providing tracking between time-critical signals.

Abstract: A memory device having an array of memory cells distributed into rows and columns with a plurality of interconnects extending across the array and coupled to carry write data during a first period of time and control data during a second period of time. In some embodiments where data I/O pads, input buffers, I/O sense amplifiers, write drivers, and color registers are collectively located on an opposite side of the array away from column decoders, column pre-decoders and column redundancy circuits, time-sharing of write data and control data on a single bus significantly improves layout efficiency.

Abstract: Methods and circuitry for implementing memory devices with I/O architectures that transmit multiple data bits on a data I/O interconnect line during a single clock cycle. Instead of increasing the physical number of I/O interconnect lines to match the increased number of data bits being processed by the multiple data rate memory circuit, a time sharing scheme is devised that processes the multiple bits of data with a minimum number of I/O lines.

Abstract: According to one embodiment, a memory device comprises a bit line operable to access a memory cell. The bit line has a first end and a second end. A first equilibration circuit is coupled to the first end of the bit line, and a second equilibration circuit is coupled to the second end of the bit line. The first and second equilibration circuits cooperate to pre-charge the bit line. According to another embodiment, an embedded-process memory device comprises a p-well and a deep n-well formed into a substrate. A retrograde well is formed into the deep n-well. An equilibration circuit for pre-charging a bit line is formed into the retrograde well.

Abstract: A memory device includes a plurality of bit lines, with each bit line serving at least one respective memory cell. A plurality of input/output lines are connected and parallel to the bit lines. The input/output lines allow data to be placed upon or extracted from the bit lines. Because the I/O lines are positioned parallel, rather than perpendicular, to the bit lines, the surface area required to implement the memory device does not increase in proportion to the number of bit lines provided. Accordingly, a relatively wide data path can be implemented on the memory device without significantly increasing the amount of surface area.

Abstract: According to one embodiment, a memory device comprises a bit line operable to access a memory cell. The bit line has a first end and a second end. A first equilibration circuit is coupled to the first end of the bit line, and a second equilibration circuit is coupled to the second end of the bit line. The first and second equilibration circuits cooperate to pre-charge the bit line. According to another embodiment, an embedded-process memory device comprises a p-well and a deep n-well formed into a substrate. A retrograde well is formed into the deep n-well. An equilibration circuit for pre-charging a bit line is formed into the retrograde well.

Abstract: In one aspect of the invention, a circuit for the hierarchical decoding of a memory device includes a local word line for accessing a memory cell. A local word line driver, which drives the local word line, has at most two transistors, each of these transistors coupled to the local word line. In another aspect of the invention, a circuit for the hierarchical decoding of a memory device includes a local word line driver for driving a local word line. A local phase line driver is connected to the local word line driver by a single metal line. The local phase line driver cooperates with the local word line driver for accessing a memory cell.

Abstract: A circuit is provided for controlling the set up of a memory address. The circuit includes a first latch circuit for latching a first memory address in response to a first simultaneous occurrence of a predetermined value for an output enable signal and a predetermined value for a row address strobe signal. A second latch circuit is coupled to the first latch circuit. The second latch circuit receives the first memory address from the first latch circuit and latches the first row address thereafter for decoding. The first latch circuit can latch a second memory address in response to a second simultaneous occurrence of the predetermined value for the output enable signal and the predetermined value for the row address strobe signal, the second simultaneous occurrence occurring while the first row address is being decoded.