Abstract: A synthesized jitter generator employing a novel digital architecture is provided. The apparatus provides period synthesis and controlled sinusoidal and non-sinusoidal jitter modulation functions of a square wave provided at its output. The architecture consists of a coupling of an N+M bit digital accumulator and an N bit synchronous counter to an N bit magnitude compare circuit. The output of the magnitude compare strobes the accumulator when the two inputs are equal in magnitude causing the accumulator to increment synchronously. The output of the magnitude compare is also a digital waveform whose average period is precisely defined by the input word to the accumulator.