Abstract: A method and apparatus for managing packet memory is provided. The apparatus includes an empty list, a storage buffer and apparatus for updating the storage buffer and empty list. The empty list includes a multiplicity of single bit buffers. The storage buffer includes a multiplicity of contiguous buffers, wherein each single bit buffer is associated with one of the contiguous buffers. The state of the bit of a single bit buffer indicates the empty or full state of the associated contiguous buffer and the address of a contiguous buffer is a simple function of the address or number of its associated single bit buffer. The updating apparatus stores data in and removes data from the contiguous buffers and correspondingly updates the states of the associated single bits buffers.

Abstract: A switched Ethernet controller (SEC) device and associated method that provides processor based intervention in the packet routing decision process is provided. The method of routing a multicast packet between a source port on a source device and a plurality of destination ports on a plurality of destination devices, utilizes a processor. The method includes the steps of the source device receiving the multicast packet via the source port, the source device sending the multicast packet to the processor, the processor examining the multicast packet, the processor determining the plurality of destination devices and corresponding the plurality of destination ports based on the results obtained during the step of examining, the processor transferring the multicast packet to the plurality of destination devices, and the plurality of destination devices sending the multicast packet to the plurality of destination ports.

Abstract: A write-only data transfer protocol for peripheral component interface busses and a method for transferring data between source and destination communication units is provided. The method includes the source communication unit writing a buffer allocation request to the destination unit and, in response to the buffer allocation request, the destination communication unit allocating space within an associated buffer to receive the data to be sent. The method also includes the destination communication unit writing at least the location of the allocated buffer to the source communication unit and the source communication unit writing the data to be sent to the allocated buffer location.

Abstract: An Ethernet controller, for use within an Ethernet network of other Ethernet controller connected together by a bus, is provided. The Ethernet controller includes a plurality of ports including at least one bus port associated with ports connected to other switching Ethernet controllers, a hash table for storing addresses of ports within the Ethernet network, a hash table address control, a storage buffer including a multiplicity of contiguous buffers in which to temporarily store said packet, an empty list including a multiplicity of single bit buffers, a packet storage manager, a packet transfer manager and a write-only bus communication unit. The hash table address control hashes the address of a packet to initial hash table location values, changes the hash table location values by a fixed jump amount if the address values stored in the initial hash table location do not match the received address, and provides at least an output port number of the port associated with the received address.

Abstract: A method and apparatus for managing packet memory is provided The apparatus includes an empty list, a storage buffer and apparatus for updating the storage buffer and empty list. The empty list includes a multiplicity of single bit buffers. The storage buffer includes a multiplicity of contiguous buffers, wherein each single bit buffer is associated with one of the contiguous buffers. The state of the bit of a single bit buffer indicates the empty or full state of the associated contiguous buffer and the address of a contiguous buffer is a simple function of the address or number of its associated single bit buffer. The updating apparatus stores data in and removes data from the contiguous buffers and correspondingly updates the states of the associated single bits buffers.

Abstract: A variable sized FIFO buffer whose size changes in accordance with how much data is present to be passed between the two systems is provided.One embodiment of the FIFO buffer includes at least one lower FIFO, at least one upper FIFO, a RAM and a controller. The upper FIFO buffer receives data from a first system and the lower FIFO buffer writes data to a second system. The RAM is utilized when data can no longer flow between the upper and lower FIFO buffers, due to the lower FIFO buffer being temporarily full.

Abstract: A multiple FIFO array which does not use numerous single FIFO devices is provided. The multiple FIFO array includes a memory partitioned into a plurality of N sections, each section corresponding to one of N FIFOs. The memory has a write address input, write strobe input, data input, read address input, read strobe and data output. Also included is a plurality of N write pointer registers, a write multiplexer having N write inputs, a write output and a write select input, a plurality of N read registers and a read multiplexer. Each write pointer register corresponds to one of N FIFOs and each write pointer register holds the write address corresponding to one of N FIFOs. The N write inputs of the write multiplexer are coupled to the output of the plurality of N write pointer registers, the write output is coupled to the write address input in the memory and the write select input couples one of the N write inputs to the write output.

Abstract: A data transfer synchronizing unit is provided for generating flags indicating the fullness state of a data transfer element. The determining unit includes the first and second counters operating according to first and second clock signals, first and second registers, serially connected to the output of the second counter, a latch unit and a comparator. The first register is clocked by the second clock signal and the second register is clocked by the first clock signal. The latch unit alternately activates the first and second registers to receive data in accordance with the second and first clock signals, respectively. The comparator produces the flags by comparing the output of the first counter with the output of the second register.