Abstract: A synchronous circuit, such as an SRAM, a DRAM or a programmable logic device, has internal circuitry, a master input latch clocked by a master clock generator, and a slave output latch clocked by a slave clock generator. The master input latch is rendered transparent prior to the start of system setup time so that information input signals can pass through the master input latch and undergo processing in the circuitry prior to the start of a system cycle. After correct and stable information output signals are generated by the internal circuitry, these signals are latched into the slave output latch as correct and stable output information. The master latch may be clocked from the latched to the transparent state before the slave latch is clocked from the transparent to the latched state, provided that the time period between these two transitions is less than the minimum processing time of the internal circuitry.
Abstract: A high speed high capacity SRAM having a density of 256K bits or larger. Individual complementary memory cell pairs are arranged in memory blocks and are directly accessed during write and read operations by input/output circuitry having an input buffer, write driver circuits, sense amplifiers, an output buffer and an output register. Data is read from individual memory blocks using a pipelined read data mode in which data accessed by a row, column and block address during a first cycle is stored in an output (pipeline) register at the beginning of the next cycle. In one embodiment all components of the data input/output circuits are located remotely from the memory blocks and paired data lines are used.