Abstract: High efficiency resonator coils for large gap resonant wireless power transfer (WPT), and a coil design methodology are disclosed. Resonator coils comprise a coil topology defined by coil parameters in which turn dimensions, such as trace widths and spacings of each turn, are configured to reduce or minimize a variance of the z component of magnetic field, over an area of a charging plane at a specified distance, or distance range, from the coil. A Tx resonator coil comprises a capacitor arrangement of tuning and network-matching capacitors for improved coil-to-coil efficiency and end-to-end WPT system performance, e.g. for applications such as through-wall WPT, in the range of tens of watts to at least hundreds of watts. Planar resonator coil topologies are compatible with fabrication using low cost PCB technology, e.g. with multi-layer metal, to reduce losses and improve thermal performance.

Abstract: Circuit-Under-Pad (CUP) device topologies for high-current lateral power switching devices are disclosed, in which the interconnect structure and pad placement are configured for reduced source and common source inductance. In an example topology for a power semiconductor device comprising a lateral GaN HEMT, the source bus runs across a center of the active area, substantially centered between first and second extremities of source finger electrodes, with laterally extending tabs contacting the underlying source finger electrodes. The drain bus is spaced from the source bus and comprises laterally extending tabs contacting the underlying drain finger electrodes. The gate bus is centrally placed and runs adjacent the source bus. Preferably, the interconnect structure comprises a dedicated gate return bus to separate the gate drive loop from the power loop. Proposed CUP device structures provide for lower source and common source inductance and/or higher current carrying capability per unit device area.

Abstract: A lateral power semiconductor device structure comprises a pad-over-active topology wherein on-chip interconnect metallization and contact pad placement is optimized to reduce interconnect resistance. For a lateral GaN HEMT, wherein drain, source and gate finger electrodes extend between first and second edges of an active region, the source and drain buses run across the active region at positions intermediate the first and second edges of the active region, interconnecting first and second portions of the source fingers and drain fingers which extend laterally towards the first and second edges of the active region. External contact pads are placed on the source and drain buses. For a given die size, this interconnect structure reduces lengths of current paths in the source and drain metal interconnect, and provides, for example, at least one of lower interconnect resistance, increased current capability per unit active area, and increased active area usage per die.

Abstract: High accuracy current sense circuitry for power switching devices comprising GaN power transistors provides for current feedback functions, e.g. current loop control, over-current protection (OCP) and short-circuit protection (SCP). The current sense circuitry comprises a current mirror sense GaN transistor (Sense_GaN) and a power GaN transistor (Power_GaN) and a sampling circuit. The sampling circuit comprises first and second stage operational amplifiers to provide fast response and improved current sense accuracy, e.g. better than 1%, over a range of junction temperatures Tj. The Sense_GaN, Power_GaN and first stage operational amplifier have a common ground referenced to a Kelvin Source of the Power_GaN, so that the Sense_GaN and Power_GaN operate with the same gate-to-source voltage Vgs, to provide an accurate current ratio. Applications include current sensing for switching mode power supplies that need high speed and lossless current sense for current protection and feedback.

Abstract: An active gate voltage control circuit for a gate driver of a power semiconductor switching device comprising a power semiconductor transistor, such as a GaN HEMT, provides active gate voltage control comprising current burst mode operation and protection mode operation. The gate-source turn-on voltage Vgs(on) is increased in burst mode operation, to allow for a temporary increase of saturation current. In protection mode operation, a multi-stage turn-off may be implemented, comprising reducing Vgs(on) to implement fast soft turn-off, followed by full turn-off to bring Vgs(on) below threshold voltage, to reduce switching transients such as Vds spikes. Circuits of example embodiments provide for burst mode operation for enhanced saturation current, to increase robustness of enhancement mode GaN power switching devices, e.g. under overcurrent and short circuit conditions, or to provide active gate voltage control which adjusts dynamically to specific operating conditions or events.

Abstract: An architecture for a multi-port AC/DC Switching Mode Power Supply (SMPS) with Power Factor Correction (PFC) comprises power management control (PMC) for PFC On/Off Control and Smart Power Distribution, and optionally, a boost follower circuit. For example, in a universal AC/DC multi-port USB-C Power Delivery (PD) adapter, PMC enables turn-on and turn-off of PFC dependent on output port operational status and a combined load of active output ports. A microprocessor control unit (MCU) receives operational status, a voltage sense input and a current sense input for each USB port, computes output power for each USB port, and executes a power distribution protocol to turn-on or turn-off PFC dependent on the combined load from each USB port. Available power may be distributed intelligently to one or more ports, dependent on load. In an example embodiment, turning-off PFC for low load and low AC line input increases efficiency by 3% to 5%.

Abstract: An AC/DC Switching Mode Power Supply (SMPS) comprises a PFC stage, an isolated LLC DC/DC converter stage, and a control circuit that provides feedback/control signals to PFC and LLC controllers, to enable a plurality of operating modes, dependent on a sensed peak AC input voltage and required output voltage Vo. The PFC provides a first DC bus voltage Vdc (e.g. 200V) for low line AC input and a second DC bus voltage (e.g. 400V) for high line or universal AC input. A multi-mode LLC converter is operable in a half-bridge mode or a full-bridge mode. For low line AC input, output voltage Vo, and PFC output Vdc, the LLC operates in full-bridge mode; for high line input, output voltage Vo and PFC output 2×Vdc, the LLC operates in half-bridge mode; for universal AC input, output voltage 2×Vo, and PFC output 2×Vdc, the LLC operates in full-bridge mode.

Abstract: A semiconductor device in provided having a substrate and a semiconductor layer formed on a main surface of the substrate. A plurality of first island electrodes and a plurality of second island electrodes are placed over the semiconductor layer. The plurality of first island electrodes and second island electrodes are spaced apart from each other so as to be alternatively arranged to produce two-dimensional active regions in all feasible areas of the semiconductor layer. Each side of the first island electrodes is opposite a side of the second island electrodes. The semiconductor device can also include a plurality of strip electrodes that are formed in the regions between the first island electrodes and the second island electrodes. The strip electrodes serve as the gate electrodes of a multi-island transistor. The first island electrodes serve as the source electrodes of the multi-island transistor. The second island electrodes serve as the drain electrodes of the multi-island transistor.

Abstract: A semiconductor device in provided having a substrate and a semiconductor layer formed on a main surface of the substrate. A plurality of first island electrodes and a plurality of second island electrodes are placed over the semiconductor layer. The plurality of first island electrodes and second island electrodes are spaced apart from each other so as to be alternatively arranged to produce two-dimensional active regions in all feasible areas of the semiconductor layer. Each side of the first island electrodes is opposite a side of the second island electrodes. The semiconductor device can also include a plurality of strip electrodes that are formed in the regions between the first island electrodes and the second island electrodes. The strip electrodes serve as the gate electrodes of a multi-island transistor. The first island electrodes serve as the source electrodes of the multi-island transistor. The second island electrodes serve as the drain electrodes of the multi-island transistor.

Abstract: A gallium nitride (GaN) device that has greatly superior current handling ability per unit area than previously described GaN devices. The improvement is due to improved layout topology. The layout scheme, which uses island electrodes rather than finger electrodes, is shown to increase the active area density over that of conventional interdigitated structures. Ultra low on resistance transistors can be built using the island topology. Specifically, the present invention, which uses conventional GaN lateral technology and electrode spacing, provides a means to enhance cost/effective performance of all lateral GaN structures.

Abstract: A fault tolerant design for large area nitride semiconductor devices is provided, which facilitates testing and isolation of defective areas. A transistor comprises an array of a plurality of islands, each island comprising an active region, source and drain electrodes, and a gate electrode. Electrodes of each island are electrically isolated from electrodes of neighboring islands in at least one direction of the array. Source, drain and gate contact pads are provided to enable electrical testing of each island. After electrical testing of islands to identify defective islands, overlying electrical connections are formed to interconnect source electrodes in parallel, drain electrodes in parallel, and to interconnect gate electrodes to form a common gate electrode of large gate width Wg. Interconnections are provided selectively to good islands, while electrically isolating defective islands. This approach makes it economically feasible to fabricate large area GaN devices, including hybrid devices.

Abstract: Devices and systems comprising driver circuits are disclosed for MOSFET driven, normally-on gallium nitride (GaN) power transistors. Preferably, a low power, high speed CMOS driver circuit with an integrated low voltage, lateral MOSFET driver is series coupled, in a hybrid cascode arrangement to a high voltage GaN HEMT, for improved control of noise and voltage transients. Co-packaging of a GaN transistor die and a CMOS driver die using island topology contacts, through substrate vias, and a flip-chip, stacked configuration provides interconnections with low inductance and resistance, and provides effective thermal management. Co-packaging of a CMOS input interface circuit with the CMOS driver and GaN transistor allows for a compact, integrated CMOS driver with enhanced functionality including shut-down and start-up conditioning for safer operation, particularly for high voltage and high current switching.

Abstract: A Gallium Nitride (GaN) series of devices—transistors and diodes are disclosed—that have greatly superior current handling ability per unit area than previously described GaN devices. The improvement is due to improved layout topology. The devices also include a simpler and superior flip chip connection scheme and a means to reduce the thermal resistance. A simplified fabrication process is disclosed and the layout scheme which uses island electrodes rather than finger electrodes is shown to increase the active area density by two to five times that of conventional inter-digitated structures. Ultra low on resistance transistors and very low loss diodes can be built using the island topology. Specifically, the present disclosure provides a means to enhance cost/effective performance of all lateral GaN structures.

Abstract: A gallium nitride (GaN) device that has greatly superior current handling ability per unit area than previously described GaN devices. The improvement is due to improved layout topology. The layout scheme, which uses island electrodes rather than finger electrodes, is shown to increase the active area density over that of conventional interdigitated structures. Ultra low on resistance transistors can be built using the island topology. Specifically, the present invention, which uses conventional GaN lateral technology and electrode spacing, provides a means to enhance cost/effective performance of all lateral GaN structures.

Abstract: A GaN-on-Si device structure and a method of fabrication are disclosed for improved die yield and device reliability of high current/high voltage lateral GaN transistors. A plurality of conventional GaN device structures comprising GaN epi-layers are fabricated on a silicon substrate (GaN-on-Si die). After processing of on-chip interconnect layers, a trench structure is defined around each die, through the GaN epi-layers and into the silicon substrate. A trench cladding is provided on proximal sidewalls, comprising at least one of a passivation layer and a conductive metal layer. The trench cladding extends over exposed surfaces of the GaN epi-layers, over the interface region with the substrate, and also over the exposed surfaces of the interconnect layers. This structure reduces risk of propagation of dicing damage and defects or cracks in the GaN epi-layers into active device regions. A metal trench cladding acts as a barrier for electro-migration of mobile ions.