Abstract: High accuracy current sense circuitry for power switching devices comprising GaN power transistors provides for current feedback functions, e.g. current loop control, over-current protection (OCP) and short-circuit protection (SCP). The current sense circuitry comprises a current mirror sense GaN transistor (Sense_GaN) and a power GaN transistor (Power_GaN) and a sampling circuit. The sampling circuit comprises first and second stage operational amplifiers to provide fast response and improved current sense accuracy, e.g. better than 1%, over a range of junction temperatures Tj. The Sense_GaN, Power_GaN and first stage operational amplifier have a common ground referenced to a Kelvin Source of the Power_GaN, so that the Sense_GaN and Power_GaN operate with the same gate-to-source voltage Vgs, to provide an accurate current ratio. Applications include current sensing for switching mode power supplies that need high speed and lossless current sense for current protection and feedback.

Abstract: Embedded die packaging for high voltage, high temperature operation of power semiconductor devices is disclosed, wherein a power semiconductor die is embedded in laminated body comprising a layer stack of a plurality of dielectric layers and electrically conductive layers. For example, the dielectric layers comprise dielectric build-up layers of filled or fiber reinforced dielectric and conductive interconnect comprises copper layers and copper filled vias. A dielectric build-up layer, e.g. filled or glass fiber reinforced epoxy, forms an external surface of the package covering underlying copper interconnect, particularly in regions which experience high electric field during operation, such as between closely spaced source and drain interconnect metal. For example, the power semiconductor device comprises a GaN HEMT rated for operation at ?100V wherein the package body has a laminated structure configured for high voltage, high temperature operation with improved reliability.

Abstract: An active gate voltage control circuit for a gate driver of a power semiconductor switching device comprising a power semiconductor transistor, such as a GaN HEMT, provides active gate voltage control comprising current burst mode operation and protection mode operation. The gate-source turn-on voltage Vgs(on) is increased in burst mode operation, to allow for a temporary increase of saturation current. In protection mode operation, a multi-stage turn-off may be implemented, comprising reducing Vgs(on) to implement fast soft turn-off, followed by full turn-off to bring Vgs(on) below threshold voltage, to reduce switching transients such as Vds spikes. Circuits of example embodiments provide for burst mode operation for enhanced saturation current, to increase robustness of enhancement mode GaN power switching devices, e.g. under overcurrent and short circuit conditions, or to provide active gate voltage control which adjusts dynamically to specific operating conditions or events.

Abstract: An architecture for a multi-port AC/DC Switching Mode Power Supply (SMPS) with Power Factor Correction (PFC) comprises power management control (PMC) for PFC On/Off Control and Smart Power Distribution, and optionally, a boost follower circuit. For example, in a universal AC/DC multi-port USB-C Power Delivery (PD) adapter, PMC enables turn-on and turn-off of PFC dependent on output port operational status and a combined load of active output ports. A microprocessor control unit (MCU) receives operational status, a voltage sense input and a current sense input for each USB port, computes output power for each USB port, and executes a power distribution protocol to turn-on or turn-off PFC dependent on the combined load from each USB port. Available power may be distributed intelligently to one or more ports, dependent on load. In an example embodiment, turning-off PFC for low load and low AC line input increases efficiency by 3% to 5%.

Abstract: An AC/DC Switching Mode Power Supply (SMPS) comprises a PFC stage, an isolated LLC DC/DC converter stage, and a control circuit that provides feedback/control signals to PFC and LLC controllers, to enable a plurality of operating modes, dependent on a sensed peak AC input voltage and required output voltage Vo. The PFC provides a first DC bus voltage Vdc (e.g. 200V) for low line AC input and a second DC bus voltage (e.g. 400V) for high line or universal AC input. A multi-mode LLC converter is operable in a half-bridge mode or a full-bridge mode. For low line AC input, output voltage Vo, and PFC output Vdc, the LLC operates in full-bridge mode; for high line input, output voltage Vo and PFC output 2×Vdc, the LLC operates in half-bridge mode; for universal AC input, output voltage 2×Vo, and PFC output 2×Vdc, the LLC operates in full-bridge mode.

Abstract: Embedded packaging for high voltage, high temperature operation of power semiconductor devices is disclosed, wherein a semiconductor die is embedded in a dielectric body comprising a dielectric polymer composition characterized by a conductivity transition temperature Tc, a first activation energy EaLow for conduction in a temperature range below Tc, and a second activation energy EaHigh for conduction in a temperature range above Tc. A test methodology is disclosed for selecting a dielectric epoxy composition having values of Tc, EaLow, and EaHigh that provide a conduction value below a required reliability threshold, e.g. ?5×10?13 S/cm, for a specified operating voltage and temperature. For example, the power semiconductor device comprises a GaN HEMT rated for operation at ?100V wherein the package body is formed from a laminated dielectric epoxy composition for operation at >150 C, wherein Tc is ?75 C, EaLow is ?0.

Abstract: Hybrid power switching stages and driver circuits are disclosed. An example semiconductor power switching device comprises a high-side switch and a low-side switch connected in a half-bridge configuration, wherein the high-side switch comprises a GaN power transistor and the low-side switch comprises a Si MOSFET. The Si—GaN hybrid switching stage provides enhanced performance, e.g. reduced switching losses, in a cost-effective solution which takes advantage of characteristics of power switching devices comprising both GaN power transistors and Si MOSFETs. Also disclosed is a gate driver for the Si—GaN hybrid switching stage, and a semiconductor power switching stage comprising the gate driver and a Si—GaN hybrid power switching device having a half-bridge or full-bridge switching topology.

Abstract: Disclosed is a method for deadtime optimization in a half-bridge switch or full-bridge switch wherein high-side and low-side switches comprise GaN transistors; a circuit for implementing the method; and a power switching system comprising a GaN half-bridge or a GaN full-bridge and a deadtime optimization system. The circuit comprises a drain current bump filter for generating a current charge output; and circuit elements for comparing the current charge output to a reference current charge Coss and generating a deadtime adjust signal. The deadtime adjust signal may be used to adjust deadtime to reduce or minimize deadtime, and deadtime losses, while avoiding cross-conduction.

Abstract: A lateral power semiconductor device structure comprises a pad-over-active topology wherein on-chip interconnect metallization and contact pad placement is optimized to reduce interconnect resistance. For a lateral GaN HEMT, wherein drain, source and gate finger electrodes extend between first and second edges of an active region, the source and drain buses run across the active region at positions intermediate the first and second edges of the active region, interconnecting first and second portions of the source fingers and drain fingers which extend laterally towards the first and second edges of the active region. External contact pads are placed on the source and drain buses. For a given die size, this interconnect structure reduces lengths of current paths in the source and drain metal interconnect, and provides, for example, at least one of lower interconnect resistance, increased current capability per unit active area, and increased active area usage per die.

Abstract: Circuit-Under-Pad (CUP) device topologies for high-current lateral power switching devices are disclosed, in which the interconnect structure and pad placement are configured for reduced source and common source inductance. In an example topology for a power semiconductor device comprising a lateral GaN HEMT, the source bus runs across a centre of the active area, substantially centered between first and second extremities of source finger electrodes, with laterally extending tabs contacting the underlying source finger electrodes. The drain bus is spaced from the source bus and comprises laterally extending tabs contacting the underlying drain finger electrodes. The gate bus is centrally placed and runs adjacent the source bus. Preferably, the interconnect structure comprises a dedicated gate return bus to separate the gate drive loop from the power loop. Proposed CUP device structures provide for lower source and common source inductance and/or higher current carrying capability per unit device area.

Abstract: Embedded die packaging for semiconductor devices and methods of fabrication wherein conductive vias are provided to interconnect contact areas on the die and package interconnect areas. Before embedding, a protective masking layer is provided selectively on regions of the electrical contact areas where vias are to be formed by laser drilling. The material of the protective masking layer is selected to control absorption properties of surface of the pad metal to reduce absorption of laser energy during laser drilling of micro-vias, thereby mitigating overheating and potential damage to the semiconductor device. The masking layer is resistant to surface treatment of other regions of the electrical contact areas, e.g. to increase surface roughness to promote adhesion of package dielectric.

Abstract: An architecture for a multi-port AC/DC Switching Mode Power Supply (SMPS) with Power Factor Correction (PFC) comprises power management control (PMC) for PFC On/Off Control and Smart Power Distribution, and optionally, a boost follower circuit. For example, in a universal AC/DC multi-port USB-C Power Delivery (PD) adapter, PMC enables turn-on and turn-off of PFC dependent on output port operational status and a combined load of active output ports. A microprocessor control unit (MCU) receives operational status, a voltage sense input and a current sense input for each USB port, computes output power for each USB port, and executes a power distribution protocol to turn-on or turn-off PFC dependent on the combined load from each USB port. Available power may be distributed intelligently to one or more ports, dependent on load. In an example embodiment, turning-off PFC for low load and low AC line input increases efficiency by 3% to 5%.

Abstract: A bulk capacitor circuit for an AC input AC/DC Switching Mode Power Supply, such as an AC/DC adapter/charger without active power factor correction, is provided, comprising a plurality of bulk capacitors having different voltage ratings, and driver and control circuitry comprising AC input voltage sensing and comparator circuitry, which enables selective connection of one or more of the plurality of bulk capacitors, responsive to a sensed AC input voltage range. A startup circuit provides power to the driver circuit initially, so that the AC input voltage can be determined before power-up and enabling of the DC/DC converter. This solution provides for a reduction in capacitor volume, with associated improvement in the power density of an isolated AC/DC power supply, while the startup circuit ensures that an appropriate bulk capacitance is connected at startup for low line AC input, to maintain the ripple voltage in an appropriate range for reliable operation.

Abstract: A circuit for a multi-voltage input AC/DC charger, such as a Universal AC input AC/DC charger, is provided, comprising a plurality of capacitors having different voltage ratings that are connected in parallel, and a switching circuit comprising input voltage sensing and comparator drive circuitry, to allow for selective connection of one or more of the plurality of capacitors, responsive to a sensed input voltage. Since bulk capacitors occupy a significant proportion of the volume of an AC/DC charger, this solution provides for a reduction in system volume, with associated improvement in the power density of an isolated AC/DC charger.

Abstract: Embedded die packaging for high voltage, high temperature operation of power semiconductor devices is disclosed, wherein a power semiconductor die is embedded in laminated body comprising a layer stack of a plurality of dielectric layers and electrically conductive layers. For example, the dielectric layers comprise dielectric build-up layers of filled or fiber reinforced dielectric and conductive interconnect comprises copper layers and copper filled vias. Where a solder resist coating is provided, a dielectric build-up layer, e.g. filled or glass fiber reinforced epoxy, is provided between the solder resist coating and underlying copper interconnect, particularly in regions which experience high electric field during operation, such as between closely spaced source and drain interconnect metal.

Abstract: Low inductance power modules for ultra-fast wide-bandgap semiconductor power switching devices are disclosed. Conductive tracks define power buses for a switching topology, e.g. comprising GaN E-HEMTs, with power terminals extending from the power buses through the housing to provide a heatsink-to-busbar distance which meets creepage and clearance requirements. Low-profile, low-inductance terminals for gate and source-sense connections extend from contact areas located adjacent each power switching device to provide for a low inductance gate drive loop, for high di/dt switching. The gate driver board is mounted on the low-profile terminals, inside or outside of the housing, with decoupling capacitors provided on the driver board. For paralleled switches, additional terminals, which are referred to as dynamic performance pins, are provided to the power buses.

Abstract: Circuit-Under-Pad (CUP) device topologies for high current lateral GaN power transistors comprise first and second levels of on-chip metallization M1 and M2; M1 defines source, drain and gate finger electrodes of a plurality of sections of a multi-section transistor and a gate bus; M2 defines an overlying contact structure comprising a drain pad and source pads extending over active regions of each section. The drain and source pads of M2 are interconnected by conductive micro-vias to respective underlying drain and source finger electrodes of M1. The pad structure and the micro-via interconnections are configured to reduce current density in self-supported widths of source and drain finger electrodes, i.e. to optimize a maximum current density for each section. For reduced gate loop inductance, part of each source pad is routed over the gate bus. Proposed CUP device structures provide for higher current carrying capability and reduced drain-source resistance.

Abstract: A GaN power switching device comprises a GaN transistor switch SW_MAIN has an integrated drain voltage sense circuit, which comprises GaN sense transistor SW_SEN and GaN sense resistor RSEN, which at turn-on form a resistive divider for sensing the drain voltage of SW_MAIN to provide a drain voltage sense output VDSEN. Fault detection logic circuitry of a driver circuit generates a fault signal FLT when VDSEN reaches or exceeds a reference voltage Vref, which triggers fast turn-off of the gate of SW_MAIN, e.g. within less than 100 ns of an overcurrent or short circuit condition. During turn-off, RSEN resets VDSEN to zero. For two stage turn-off, the driver circuit further comprises fast soft turn-off circuitry which is triggered first by the fault signal to pull-down the gate voltage to the threshold voltage, followed by a delay before full turn-off of the gate of SW_MAIN by the gate driver.

Abstract: GaN HEMT device structures and methods of fabrication are provided. A masking layer forms a p-dopant diffusion barrier and selective growth of p-GaN in the gate region, using low temperature processing, reduces deleterious effects of out-diffusion of p-dopant into the 2DEG channel. A structured AlxGa1-xN barrier layer includes a first thickness having a first Al %, and a second thickness having a second Al %, greater than the first Al %. At least part of the second thickness of the AlxGa1-xN barrier layer in the gate region is removed, before selective growth of p-GaN in the gate region. The first Al % and first thickness are selected to determine the threshold voltage Vth and the second Al % and second thickness are selected to determine the Rdson and dynamic Rdson of the GaN HEMT, so that each may be separately determined to improve device performance, and provide a smaller input FOM (Figure of Merit).

Abstract: A GaN-on-Si device structure and a method of fabrication are disclosed for improved die yield and device reliability of high current/high voltage lateral GaN transistors. A plurality of conventional GaN device structures comprising GaN epi-layers are fabricated on a silicon substrate (GaN-on-Si die). After processing of on-chip interconnect layers, a trench structure is defined around each die, through the GaN epi-layers and into the silicon substrate. A trench cladding is provided on proximal sidewalls, comprising at least one of a passivation layer and a conductive metal layer. The trench cladding extends over exposed surfaces of the GaN epi-layers, over the interface region with the substrate, and also over the exposed surfaces of the interconnect layers. This structure reduces risk of propagation of dicing damage and defects or cracks in the GaN epi-layers into active device regions. A metal trench cladding acts as a barrier for electro-migration of mobile ions.