Patents Assigned to Garrett Electronics, Inc.
  • Patent number: 4709213
    Abstract: A metal detector circuit includes a transmit coil (12) and a receive coil (56) arranged in a balanced induction configuration in an electromagnetic field. The receive signal from the receive coil (56) is input to electronic switches (146, 148) which receive quadrature reference inputs from a phase shift circuit (112). The phase demodulated outputs of the switches (146, 148) are passed through amplifiers and input to an analog-to-digital converter (324) to produce digital signal samples which are transmitted through a bus (326). The bus (326) is connected to random access memory (414, 416) and a read only memory (418) which includes a stored signal processing program. A microprocessor (374) is connected to the bus (376) for receiving the digital signal samples and the stored program from memory (418). The microprocessor (374) executes the stored signal processing program to produce a digital output signal which is transmitted through the bus (326) to a digital-to-analog converter (360).
    Type: Grant
    Filed: July 8, 1985
    Date of Patent: November 24, 1987
    Assignee: Garrett Electronics, Inc.
    Inventor: Robert J. Podhrasky
  • Patent number: 4700139
    Abstract: A metal detector circuit of the balanced induction type is utilized to detect hidden metal objects. A receive signal is provided with two fixed concurrent phase shifts relative to the transmit signals. Each of the phase shifted receive signals is synchronously demodulated to produce first and second vector signals. The vector signals are combined in a summation circuit to produce a third vector signal. The first and third vector signals are then selectively combined by an operator to produce a fourth vector signal having a desired vector range between minimum and maximum vector angles. The metal detector circuit of the present invention provides a response for objects having a phase response signal outside the selected phase range. The first and fourth vector signals are each differentiated twice then level detected. The outputs from the level detection process are logic signals which are input to an AND gate.
    Type: Grant
    Filed: October 29, 1984
    Date of Patent: October 13, 1987
    Assignee: Garrett Electronics, Inc.
    Inventor: Robert J. Podhrasky
  • Patent number: D297221
    Type: Grant
    Filed: October 28, 1985
    Date of Patent: August 16, 1988
    Assignee: Garrett Electronics, Inc.
    Inventor: Robert J. Podhrasky