Patents Assigned to Gates Technology
  • Publication number: 20140081875
    Abstract: A method executed at least in part in a computing device for providing cloud based customer support services includes providing a cloud based service enabling data interchange between participants of a cloud based support service, the participants including customers seeking support on products or services and support personnel from companies providing the products or services. The method further includes associating a subset of the participants with a selected product or service, enabling the customers to initiate a support case for the selected product or service, and enabling the subset of the participants associated with the product or service to communicate in order to resolve the support case.
    Type: Application
    Filed: September 13, 2013
    Publication date: March 20, 2014
    Applicant: New Gate Technologies, Inc.
    Inventors: Eric Pierson, Kellen Pierson, Bruce Pierson, Adriele Rosheger
  • Patent number: 8549450
    Abstract: Methods and software for determining one or more boundary conditions for nets in a signal path are disclosed. The method generally includes determining an expected characteristic for at least one net in the signal path and determining a boundary characteristic for that net. Determining a boundary characteristic for the net may include multiplying the expected characteristic by a scaling factor to produce a scaled characteristic for the net, performing timing analysis of the signal path in accordance with the scaled characteristic (e.g., by calculating timing while assuming that the net has the scaled characteristic), determining if the signal path violates a timing constraint when the net has the scaled characteristic, and repeating the determination with a new scaled characteristic if timing is violated. Advantageously, maximum and/or minimum values may be determined for characteristics of signal path nets that still satisfy timing constraints.
    Type: Grant
    Filed: May 31, 2011
    Date of Patent: October 1, 2013
    Assignee: Golden Gate Technology, Inc.
    Inventor: Michael Burstein
  • Patent number: 8468488
    Abstract: Methods and software for methods and software for placing and routing a signal path in an integrated circuit layout are disclosed. The signal path generally includes a plurality of cells and combinational paths having at least one net between said cells. The method includes determining whether an adjacent cell can be swapped with a selected cell (e.g., where the selected cell is one of the cells of the signal path and the adjacent cell is adjacent to the selected cell in the layout), determining whether a delay of the signal path decreases after swapping positions of the adjacent cell and the selected cell, and determining whether swapping the adjacent and selected cells causes a timing violation in another signal path of the layout. The present invention advantageously provides an automated method of improving the timing characteristics of poorly performing signal paths, without causing timing violations in other signal paths in the same integrated circuit.
    Type: Grant
    Filed: May 31, 2011
    Date of Patent: June 18, 2013
    Assignee: Golden Gate Technology, Inc.
    Inventor: Michael Burstein
  • Patent number: 8370786
    Abstract: Methods and software for placing or re-placing integrated circuit cells and routing or re-routing nets between the cells in an integrated circuit layout. The method includes selecting a region of the cells in the integrated circuit layout, selecting a cell within the selected region, locating a border point where a net coupled to the selected cell crosses a border of the selected region, and moving the selected cell within the selected region to improve a timing characteristic (e.g., a wire length, capacitance, or other characteristic of the net that affects timing or delay) of the net. The method and software advantageously improve the placement of cells and routing of wires around congested or reserved regions after global routing has been performed, without causing timing violations in other signal paths on the integrated circuit device, in a computationally efficient manner.
    Type: Grant
    Filed: May 31, 2011
    Date of Patent: February 5, 2013
    Assignee: Golden Gate Technology, Inc.
    Inventor: Michael Burstein
  • Patent number: 8225669
    Abstract: A method for ultrasonic testing includes placing an ultrasonic probe in a liquid bath inside of a pressure vessel having an elastomeric diaphragm stretched across an opening of the pressure vessel, applying pressure within the pressure vessel to bring the elastomeric diaphragm towards a test piece, and conducting ultrasonic testing of the test piece using the ultrasonic probe. A device for ultrasonic testing of a test piece includes a pressure vessel having an elastomeric diaphragm and an ultrasonic probe disposed within the pressure vessel.
    Type: Grant
    Filed: May 1, 2008
    Date of Patent: July 24, 2012
    Assignee: New Gate Technologies
    Inventor: Eric Pierson
  • Patent number: 8185860
    Abstract: A method, algorithm, software, architecture and/or system for routing signal paths or connections between circuit blocks in a circuit design is disclosed. In one embodiment, a method of routing can include: (i) determining a signal path between at least three circuit blocks; (ii) placing a routing guide; and (iii) routing the signal path through the routing guide such that a timing of a signal along the signal path at two or more the circuit blocks is substantially matched. The circuit blocks can include standard cells configured to implement a logic or timing function, other components, and/or integrated circuits, for example. The routing guide can include a splitter configured to branch the signal path into at least two associated segments. Embodiments of the present invention can advantageously improve signal timing for high fanout signal paths between circuit blocks in an automated place-and-route flow.
    Type: Grant
    Filed: August 9, 2011
    Date of Patent: May 22, 2012
    Assignee: Golden Gate Technology, Inc.
    Inventors: Michael Burstein, Boris Ginzburg, Andrew Nikishin
  • Patent number: 8015533
    Abstract: A method, algorithm, software, architecture and/or system for routing signal paths or connections between circuit blocks in a circuit design is disclosed. In one embodiment, a method of routing can include: (i) determining a signal path between at least three circuit blocks; (ii) placing a routing guide; and (iii) routing the signal path through the routing guide such that a timing of a signal along the signal path at two or more the circuit blocks is substantially matched. The circuit blocks can include standard cells configured to implement a logic or timing function, other components, and/or integrated circuits, for example. The routing guide can include a splitter configured to branch the signal path into at least two associated segments. Embodiments of the present invention can advantageously improve signal timing for high fanout signal paths between circuit blocks in an automated place-and-route flow.
    Type: Grant
    Filed: September 21, 2004
    Date of Patent: September 6, 2011
    Assignee: Golden Gate Technology, Inc.
    Inventors: Michael Burstein, Boris Ginzburg, Andrew Nikishin
  • Patent number: 7823112
    Abstract: A method, software, and system for placing circuit elements and routing wires. The method, software, and system generally include the steps of (a) determining a boundary condition for signal paths between components in a circuit, wherein each of the components receives a clock signal and the signal paths include n wires and (n?1) circuit elements in alternating serial communication between the components, n being 2 or more; and (b) placing the circuit elements and routing the wires between the comments and the circuit elements such that no signal path in the circuit exceeds the boundary condition. In preferred embodiments, the boundary condition is a maximum length, and the method further includes placing the clocked components in a floor plan such that no signal path can exceed the boundary condition. The present invention advantageously ensures that timing requirements for signal paths between clocked circuit components are met automatically.
    Type: Grant
    Filed: May 30, 2003
    Date of Patent: October 26, 2010
    Assignee: Golden Gate Technology, Inc.
    Inventors: Mikhail Makarov, Igor Chourkin, Mikhail Komarov, Boris Ginzburg
  • Patent number: 7360193
    Abstract: A method, algorithm, software, architecture and/or system for placing circuit blocks and/or routing wires in a circuit design is disclosed. In one embodiment, a method of placing can include: (i) determining a first signal path between first and second circuit blocks and determining a second signal path between first and third circuit blocks; and (iii) placing the first circuit block relative to the second and third circuit blocks in a position related to a switching activity of the first and second signal paths. The circuit blocks can include standard cells configured to implement a logic function, other components, or integrated circuits, for example. The switching activity can include a switching frequency determination based on simulation results of the first and second signal paths between the circuit blocks. Embodiments of the present invention can advantageously reduce power consumption as well as supply noise by optimally placing circuit blocks in an automated place-and-route flow.
    Type: Grant
    Filed: September 21, 2004
    Date of Patent: April 15, 2008
    Assignee: Golden Gate Technology, Inc.
    Inventors: Michael Burstein, Mikhail Komorov, Georgy Sergeev
  • Patent number: 7260804
    Abstract: A method, algorithm, software, architecture and/or system for routing signal paths or connections between circuit blocks in a circuit design is disclosed. In one embodiment, a method of routing can include: (i) determining a switching activity for signal path between a first circuit block and a second circuit block; and (ii) routing the signal path substantially in a connectivity layer related to the switching activity of the signal path. The circuit blocks can include standard cells configured to implement a logic or timing function, other components, and/or integrated circuits, for example. The switching activity can include a switching frequency determination based on simulation results of the signal path between the circuit blocks. Embodiments of the present invention can advantageously reduce power consumption as well as supply noise by optimally routing signal paths between circuit blocks in an automated place-and-route flow.
    Type: Grant
    Filed: September 21, 2004
    Date of Patent: August 21, 2007
    Assignee: Golden Gate Technology, Inc.
    Inventors: Michael Burstein, Vladimir Zakladny, Alexander Kouznetsov
  • Patent number: 7183899
    Abstract: A remotely monitored and controlled building automation system is disclosed providing efficient offsite use of BAS personnel to monitor and control such systems while utilizing relatively inexpensive alarm monitoring services to advice of system emergencies. In a first preferred embodiment, the building automation system transmits a simplified BAS/energy alarm (including only building identity information) via a specially adapted and configured local security panel to an offsite monitoring center. Thereafter, the alarm is re-transmitted to a BAS web server and on to a BAS website. The BAS website provides notification of the energy alarm to trained BAS technicians located at a remote dealer and enables such personnel, via the website to maintain two-way communication with the building automation system from which the alarm originated. Such personnel are thereby enabled to fully analyze and properly respond to the circumstances which resulted in the alarm.
    Type: Grant
    Filed: March 15, 2004
    Date of Patent: February 27, 2007
    Assignee: Global Gate Technologies, Inc.
    Inventor: Walter C. Behnke
  • Patent number: 7178124
    Abstract: A method, algorithm, software, architecture and system for placing circuit components and routing wires. The method and algorithm generally include (a) placing components in an array of allowed locations, wherein each of the components receives a clock signal and each of the allowed locations is about the same distance from a first nearest neighbor along at least a first axis as are other allowed locations along said first axis, and (b) one of the following: (i) independently routing a plurality of combinational paths from at least two components to at least two other components, (ii) routing the clock signal to the components, or both (i) and (ii). The present method, algorithm, software, architecture and system advantageously reduce power and/or current consumption in integrated circuits, improve uniformity of timing for signal paths between clocked circuit components, and/or ensure that timing requirements for signal paths between clocked circuit components are met automatically.
    Type: Grant
    Filed: May 30, 2003
    Date of Patent: February 13, 2007
    Assignee: Golden Gate Technology, Inc.
    Inventors: Mikhail Makarov, Igor Chourkin, Mikhail Komarov, Boris Ginzburg
  • Patent number: 6278740
    Abstract: Differential signaling between integrated circuit chips uses fewer than 2 external wires per bit transmitted. Rather than pairing wires into groups of two, the external wires are part of a larger group of 2i+2 wires. Half of the wires in the group are driven low while the other half of the wires are driven high. Since the wires are not paired, adjacent wires can have the same logical state. Differential comparators in the receiver chip compare each wire with all other wires in the group. All outputs of comparators that have a wire as one of its two inputs are input to a majority logic block that evaluates the logical state of the wire. Since half of the wires are in one state, the majority of the remaining wires are in the opposite state of the wire being evaluated. Thus the majority of the comparator outputs indicate the opposite state of the wire being evaluated.
    Type: Grant
    Filed: November 19, 1998
    Date of Patent: August 21, 2001
    Assignee: Gates Technology
    Inventor: Keith D. Nordyke
  • Patent number: 6238078
    Abstract: Chemical reaction is effected utilizing light of an appropriate frequency supplied preferably via optical fibers to one or more light extractors having light-emissive surfaces in contact with reactants. The light can be concentrated before being delivered. Wave guides and a plurality of such extractors can be provided within the vessel.
    Type: Grant
    Filed: December 6, 1999
    Date of Patent: May 29, 2001
    Assignee: Gate Technologies International, Inc.
    Inventor: Aharon Zeev Hed
  • Patent number: 6043294
    Abstract: Chemical reaction is effected utilizing light of an appropriate frequency supplied preferably via optical fibers to one or more light extractors having light-emissive surfaces in contact with reactants. The light can be concentrated before being delivered. Wave guides and a plurality of such extractors can be provided within the vessel.
    Type: Grant
    Filed: January 29, 1998
    Date of Patent: March 28, 2000
    Assignee: Gate Technologies International, Inc.
    Inventor: Aharon Zeev Hed