Abstract: A multiple chip self-aligning clock distribution system. The clock signal provided to any given chip is delayed by the on-chip distribution time of every other chip with which it is to be synchronized. Equal delay paths are added to each chip which provide a delay equal to the clock distribution delay of the chip. The equal delay paths can comprise a series of logic gates, such as for example inverters. The clock distribution delay of the equal delay path is designed to be equal to the clock distribution delay of the clock distribution tree on the chip. For each chip to be synchronized, the clock signal is routed through an equal delay path on each of the other chips to be synchronized before being coupled to the clock distribution input terminal of the destination chip. The number of equal delay paths that is included on each chip is a function of the number of chips to be synchronized. "N" equal delay paths are used where the number of chips is greater than 2.sup.N-1 and is less than or equal to 2.sup.N.

Abstract: A new class of shift registers that shift the contents of a 2.sup.n bit length register up to 2.sup.n -1 positions in n cycles. Shift registers according to the present invention can be constructed to shift left, shift right, or to shift either left or right. A general implementation of this class of shift registers comprises the following hardware: 2.sup.n D flip-flops or D latches for the data register positions of the shift register; logic for each of the 2.sup.