Abstract: An integrator is described that is useful in forming low pass, band pass, high pass, and band stop filters. The integrator comprises a transconductance amplifier and a capacitor which is connected between the amplifier output terminal and the amplifier ground. When implemented as a monolithic IC, the integrator gain is fundamentally process independent. A ladder structure comprising one or more of these integrators provides high order filtering characteristics without many of the problems associated with conventional filter devices. In addition, the integrator provides stop band, zero filter characteristics at the filter output terminal when a capacitor is connected across the differential input terminals of the integrator.

Abstract: A circulating FIFO buffer eliminates the need to move the data through the register and relies instead on input and output counters to load data into the register and read data therefrom. Apparatus comprises an addressable read/write memory, an input counter and an output counter, both of which address the memory, means for resetting the counters, means for enabling the input counter to increment and to load data into the buffer, means for enabling the output counter after a predetermined amount of data has been loaded into the buffer, means for disabling the input counter when the buffer register has been loaded and means for detecting when the outputs of the output and input counters are equal and for activating the resetting means upon detecting such equality.

Abstract: A method and apparatus are described for automatically placing a modem in the answer or originate mode of operation without the use of a ring detector or a manually operated answer/originate mode selection switch. A timer and two latches are connected in the modem in such a fashion that when the modem is switched into operation it is in the originate mode. For a period of time determined by the timer, the modem looks for the receipt of an answer tone from a remotely located modem. If the answer tone is detected within this time, the modem remains in the originate mode and completes a handshaking sequence with the remote modem. If, however, the answer tone is not received, the modem automatically switches to the answer mode of operation and transmits an answer tone as part of the handshaking sequence.

Abstract: A method and apparatus are described for automatically generating the frame that is used in a bit-interleaved time division multiplexer (TDM). The apparatus comprises a microprocessor, two random access memories in which are stored the channel select signals, device for determining the transmission frequencies of each channel and a computer program which is stored in the memory of the computer for calculating the distribution of the channel select signals in the frame. With such a system, the frame can be reconfigured in about thirty seconds. Two random access memories are preferably used for the storage of the channel select signals. While the signals stored in one memory are being used to generate the actual frame, a new set of channel select signals can be stored in the other memory. After such an updated frame is written in the second memory, the task of generating the channel select signals can be switched from the first memory to the second memory without loss of any data from any of the data channels.

Abstract: A synchronization technique in which the frame used for synchronization is different from that used for normal data communiction and contains few if any bits other than those used to establish synchronization. At the beginning of data communication, the synchronization frame is stored in one of a pair of memories and this frame is read out of the memory onto a communication channel between the local and remote stations. At the same time, the other memory is used to store the frame that is normally used for data communication. When synchronization is established between the local and remote stations, signal generation shifts from the first memory to the second; and the second memory immediately begins to produce the channel select and overhead signals needed for data communication. Illustratively, the synchronization frame contains less than one hundred bits and in a preferred embodiment a total of forty-eight bits are used for synchronization.

Abstract: A method and apparatus are described in which the control signals for a data channel are transmitted along with the channel aaddress. The control signal and its address are transmitted on a bit interleaved basis in response to CONTROL select signals that are generated as part of the frame. In accordance with the invention, the CONTROL select signals are distributed relatively uniformly throughout the frame. At the receiver, the bits of the control signal and its address are reassembled and the address is used to route the control signal to its proper channel. Further, the bandwidth assigned to control signaling is increased by inserting CONTROL select signals in all time slots that are available in the frame after the necessary channel select signals and other overhead select signals have been assigned. This technique is particularly advantageous in a system having a fixed aggregate transmission bandwidth, variable loads and the capability of automatically reconfiguring the frame.

Abstract: A method and apparatus are described for ensuring that control signals from every data channel are transmitted periodically regardless of any change in these control signals. The apparatus comprises a counter for counting the number of control signals transmitted, decision logic for determining when it is time to transmit a set of control signals regardless of any change in these signals and circuitry for selecting the channel whose signals are to be transmitted. The apparatus provides additional equipment for determining when the control signals for a particular channel have changed and for transmitting such signals with suitable error checking. The apparatus also provides equipment for interleaving the two flows of control signals without loss of the control signals which are changed.

Abstract: A clock rate generator is described which can be programmed to provide an output clock rate that is N/M times the rate of a standard clock where N and M are integers. The generator comprises a counter, a programmable memory, reset logic and a clocking control. A standard clock is applied to the counter so that the counter is advanced by one for each clock bit. The output of the counter is connected to the input lines of the programmable memory where a pattern of binary ones and zeros are stored. The output of the programmable memory is applied to the clocking control to combine successive bits of the same polarity. The divisor M is determined by the number of standard clock counts between successive resets of the counter. The multiplier N is determined by the number of output cycles from the clocking control between successive resets of the counter.

Abstract: A transistorized keying circuit is described which provides for both polar and neutral interfacing. The circuit comprises an oscillator, an AND gate, an exclusive OR gate, a transformer, and two similar output circuits each of which is connected to the secondary of the transformer. The oscillator produces a high frequency binary output signal having an asymmetric duty cycle. The output of the oscillator and a low frequency data signal are applied to the AND gate. The output of the AND gate and another low frequency data signal are applied to the exclusive OR gate whose output is amplified and applied to the primary of the transformer. Each output circuit coupled to the secondary of the transformer comprises a switching transistor for switching a supply voltage onto a transmission line and a peak detector for controlling the operation of the switching transistor.

Abstract: A method and apparatus are disclosed which provide a common handshaking protocol for the 201, 202 and 208 modems. In accordance with the invention, connection of answer modem and originate modem to the communication line is followed by a period of silence that is sufficiently long to reactivate any echo suppressors in the communication line. Thereafter at least two training sequences are transmitted, one from the originate modem to the answer modem and the other from the answer modem to the originiate modem, each training sequence being sufficiently long to train up any echo canceller in the line. The lengths of the training sequences as received are compared with their lengths as transmitted to determine if the length of the sequence was shortened by an echo suppressor. If the length of the training sequences as received are significantly shorter than their lengths as transmitted, a sacrificial carrier is transmitted at the beginning of each transmission of data in a new direction.

Abstract: Portions of an adaptive equalizer can be used for exact preamble synchronization by modifying the digital filter section to recognize pre-determined sequences of signals in the received signal. This may be accomplished by applying to the modifying means of the digital filter input signals which are proportional to the complex conjugate of the signals in the received signal. When the signals in the tapped delay line are aligned with this complex conjugate, the output of the summing means will be discernibly greater than otherwise. As a result, a threshold device can be used to recognize the exact baud time the preselected signals in the received signal are contained in the tapped delay line.

Abstract: A method and apparatus are described for generating a sequence of signals using first and second read-only memories, a counter associated with each memory as an address register, a source of timing signals connected to the input of each counter, decoding apparatus for the output of each memory and control logic to enable only one memory at a time. The two memories are organized in hierarchical fashion so that the first memory controls the second. Advantageously, the first memory provides for generation of unique portions of the sequence while the second memory provides for generation of repeated portions of the sequence.

Abstract: A method and apparatus are disclosed for using a specified pattern of signal events for signaling in a digital communication system. Illustratively, detection of a first event in a control signal activates timing apparatus which looks for a second event in a control signal within a specified time "window" and at least one additional event in either a data or a control signal within a specified time period. Preferably, the first event is a drop in one of the carrier detect or request to send signals and the second event is a rise in the same signal. The additional event illustratively is reception of two identical data characters, each representing an address and an operation code. Each of these two characters must be received and compared for verification within the specified time period in order to produce an output control signal decoded from the operation code.

Abstract: A method and apparatus are disclosed for closed loop testing of first and second modulators and demodulators from the modulated signal side of the first modulator and first demodulator. During ordinary communication, the first modulator and second demodulator are connected in series and the first demodulator and the second modulator are connected in series. In response to each test initiate signal, a loop is established between the second modulator and the second demodulator on their modulated signal side. Upon reception of some test initiate signals, a loop is established between the first modulator and first demodulator on their demodulated side and they are disconnected from the second demodulator and second modulator.

Abstract: A data communication system is described in which dial access control signals such as RING, DATA SET READY, DATA TERMINAL READY, CARRIER DETECT, and OUT OF SERVICE are transmitted between a central processing unit (CPU) and remote terminals in the form of frequency-modulated signals. A special frequency signal is transmitted from a remote terminal whenever a RING or DATA SET READY control signal is present and a CARRIER DETECT signal is not. Preferably, this special frequency is midway between the center frequency used for data communication and the frequency of either the MARK or the SPACE signal. Upon reception, this special frequency signal is processed in a particular fashion to generate signals comparable to the RING or DATA SET READY signals of the prior art. DATA TERMINAL READY and CARRIER DETECT control signals are transmitted as carrier signals and the OUT OF SERVICE signal is transmitted as a center frequency signal.