Abstract: In a communication network (20), a video encoder/decoder system (114) and an encoding method (150) facilitate transmission of video frames (116) over multiple low-data-rate channels (46). Frame data (204) is generated for each video frame (116). The frame data (204) is transformed (172) to obtain transform coefficients (212), which are assembled (174) into quadtrees (216) and separately coded (178). In addition, motion vectors (166) are split into coding blocks (188) and separately coded (190). The quadtrees (126) and the motion vectors (166) are independently distributed among the multiple channels (46) for transmission. A decoding method (360) facilitates error resilient reception of transform coefficient packets (222) and motion vector packets (244) so that lost transform coefficients (374) and/or lost motion vectors (384) can be estimated at a receiving video encoder/decoder system (114) to reconstruct a received video frames 144.

Abstract: In a wireless communication system (20) configured for default communication of subsectional signals of a first transmit signal (72/73) over multiple wireless channels (46), a signal selector (82) and method (138) detect an intent to convey a voice signal (86) over one of the wireless channels (46) from a handset (58). The signal selector (82) and method (138) prevent communication of one of the subsectional signals (72A) over the wireless channel (46) for a predetermined interval, and enable a transmission attempt of the voice signal (86). When a complete dialed digits sequence is detected within the time interval, the handset (58) is enabled to utilize the wireless channel. However, when a transmission attempt of the voice signal (86) is unsuccessful or when transmission of the voice signal (86) terminates, the signal selector (82) and method (138) restore default communication of subsectional signals of the first transmit signal (72/73).

Abstract: Embodiments of the present invention are directed to a satellite communications system between satellites and terminal units that are sufficiently small to be handheld units and that operate within the earth power flux density limit. This is accomplished by using spreading spectrum waveform protocols that make efficient use of the allocated bandwidth. In one embodiment, a satellite communications system comprises at least one satellite, and at least one ground station each corresponding to one of the at least one satellite. Each ground station includes a spread spectrum transmitter and a spread spectrum receiver. Each of a plurality of mobile terminals includes a spread spectrum transmitter and a spread spectrum receiver.

Abstract: An amplification circuit (10) is used in a radio receiver (12) to achieve both constant phase shift over the gain range and low intermodulation. A gain-controlled amplifier (16) is desirably optimized for good fidelity, even if at the expense of poor phase linearity. A phase shift compensator (48) compensates for phase non-linearity by imposing a delay of variable duration downstream of the gain-controlled amplifier (16). The delay duration is determined in response to a gain-control signal (20) generated by an AGC circuit (42). The gain-control signal (20) is translated through a look-up table (62) into delay values which control a programmable delay element (64). The programmable delay element (64) generates an adjusted clock signal (54) that drives a digitizer (36). The digitizer (36) both digitizes and delays an amplified signal (32) produced by gain-controlled amplifier (16).

Abstract: A hardware resource identifier (19) recognizes hardware resource dependencies in a multi-channel communications system. Initially, system communications domains (D1-D4) in which system hardware resources are located are identified. Next, managed hardware resources, hardware resource groups and hardware resource group boundaries among the system hardware resources are identified. Association labels are then assigned to the system hardware resources to identify relationships, if any, between the system hardware resources and external hardware, to discern redundant resources within respective ones of the hardware resource groups, and to characterize dedicated coupling between individual ones of the system hardware resources.

Abstract: Apparatus and methods are provided for object recognition and compression. The apparatus (114) comprises an object processor (402) configured to receive the image (120) and synthesize a contour (404) of an object within the image (120) and a classification engine (406) configured to receive the contour (404) of the image (120) and recognize the object within the image as a member of a first object class if the object substantially meets first object criteria of the first object class that is at least partially related to the target-specific utility of the image. The apparatus (114) also comprises a multi-rate encoder (116) configured to compress a first region of the image (120) having said object recognized as said member of said first object class at a first coding rate, said first coding rate providing a first coding resolution of said first region that is greater than a second coding resolution provided by a second coding rate for the image.

Abstract: A low-power digital communications transmitter (20) includes a programmable digital-processing circuit (22), which may be provided by a digital signal processor (DSP), a programmable direct digital synthesizer (DDS), and a constant-envelope, high power amplifier (32). The DDS (24) is programmed to provide pulse-shaping and IF/RF signal modulation functions. The digital-processing circuit (22) produces only one sample per unit interval (134) and is programmed so that the one sample per unit interval (134) is a frequency-profile index symbol (52?) produced from a I,Q baseband symbol (52?). The DDS (24) converts each frequency-profile index symbol (52?) into a frequency profile (130) that controls the frequency of a synthesizer (56) to induce modulation into a periodic output (68) of the synthesizer. Moreover, the frequency profile (130) is configured to confine spectral emissions within a spectral mask (140).

Abstract: A software-defined radio (12) includes a transmitter (20) having any number of upstream modules (30) and any number of downstream modules (34). The upstream modules (30) perform signal processing on input signals (28), and the downstream modules (34) provide an RF interface for processed signals (58). The upstream modules (30) and downstream modules (34) couple to a common intra-transmitter signal transporter (32), which may be implemented as a bus. Programmable transmission parameters (60) which program the downstream modules (34) to generate a communication signal (18) exhibiting desired attributes such as frequency and keying are mingled with the processed input signal (58) in upstream modules (30) to preserve timing. The programmable transmission parameters (60) are extracted in downstream modules (34), and applied to the communication signal (18) at the timing specified by position relative to the processed input signal (58).

Abstract: A voltage-controlled oscillator in which a tunable resonator (102) having a first port (132) and a second port (106) is disclosed. In one embodiment, the tunable resonator is a series resonating circuit having low driving and load impedances. A power gain element (108) is coupled to the first port and the second port, and an output port (110) is coupled to the power gain element and the second port. The first impedance at the first and second ports is less than approximately ten ohms. The voltage-controlled oscillator is capable of generating a signal at the output port of greater than approximately half a watt.

Abstract: A symbol synchronizer (100) is provided for a software-defined communications system (10). The symbol synchronizer (100), when integrated into either a pre- or post-detection diversity signal combiner (108, 208), enables highly accurate signal synchronization with minimal added system complexity. The symbol synchronizer (100) includes a single complex sliding window matched filter (102) for filtering an input digital signal with a match filtering function based on predetermined signal transfer function characteristics to average out receiver noise from the signal. A signal delay bank (84) includes a plurality of delay blocks each for delaying the digital signal filtered by the single matched filter for a predetermined number of samples. A complex correlator (88) correlates the digital signal filtered by the single complex sliding window matched filter (102) and delayed by the complex correlator (88) with a correlator reference signal, and selects an index of a path having a peak correlator value.

Abstract: A method and system for detecting GPS interference is disclosed. In one exemplary embodiment, a method for detecting interference in a Global Positioning System comprises the steps of receiving at least one satellite signal from one or more satellites in a Global Positioning System; identifying a noise floor value from the at least one satellite signal; identifying an interference signal based on the noise floor value; determining an interference value for the interference signal from the noise floor value wherein a level of the noise floor value corresponds to a level of interference; and providing the interference value to at least one user for informing the user of the interference signal.

Abstract: A signal calibrator (14) for a software-defined communications device (10) that enables device communications signals to be transmitted in a manner that maximally decouples the calibrator (14) from the device hardware (40), and that simplifies the design and reduces the cost of the communications device (10). The calibrator (14) includes a software modulator (16) for generating a nonstop stream of samples including zero valued samples and non-zero valued waveform bursts, and a software demodulator (18) connected to the software modulator (16) via a closed loop feedback path (20) that receives a nonstop stream of samples. The non-zero valued samples create radio emissions. The software demodulator (18) is for determining a timing error of the transmission sample and for transmitting a timing error correction value to the software modulator (16) via the closed loop feedback path (20).

Abstract: A software-defined radio includes a communications security processor (221) configured to transmit and receive a plurality of waveforms under a plurality of communications standards, and a reconfigurable resource configured to execute a plurality of software programs. Each of the software programs is capable of reconfiguring the reconfigurable resource to emulate one of a plurality of processors to process a portion of the plurality of waveforms under one of the plurality of communications standards. The reconfigurable resource is implemented on a single chip. In one embodiment, the reconfigurable resource is a field programmable gate array (301). In the same or another embodiment, at least one of the plurality of processors is a digital signal processor (400, 500, 700, 1000).

Abstract: An active signal suppression system utilizes multi-rate recombinant transmultiplexer (56) to suppress or cancel an undesired signal (46) from a wideband composite signal (40) to be applied to an analog to digital converter (20). The transmultiplexer (56) includes a first demultiplexer (88,90), multiplier (100), switch (120), and multiplexer (128,130). The demultiplexer and multiplexer each have a poly phase filter and Fast Fourier Transform pair which permit channelization and facilitate the generation of a cancellation signal (145) for suppression of the undesired signal. Signal cancellation circuit (60) receives the composite signal (40) at one input (70) and the cancellation signal (145) at another input (76). A minimum mean square estimation circuit (MMSE) (158) and a second demultiplexer (145, 146) are included in a feedback circuit to provide error correction.

Abstract: A direct conversion receiver includes a differential mode mixer with first and second DC coupled amplifier chains, the first and second amplifier chains are connected to the mixer for amplifying differential signals. A common mode offset correction circuit is coupled to the first and second amplifier chains so as to feedback correction signals that cause common mode DC offsets in the first and second amplifier chains to be equal and opposite. A differential mode offset correction circuit is coupled to the first and second amplifier chains so as to feedback correction signals that cause differential mode DC offsets in the first and second amplifier chains to be equal. The only solution for the two correction circuits is zero DC offset.

Abstract: A computer-implemented system (90) is provided that supports a high degree of separation between processing elements. The computer-implemented system (90) comprises a plurality of cells (92) residing on the computer-implemented system, where each cell (92) includes a domain of execution (94) and at least one processing element (96); a separation specification (99) that governs communication between the processing elements (96); and a kernel (98) of an operating system that facilitates execution of the processing elements (96) and administers the communication between the processing elements (96) in accordance with the separation specification (99), such that one processing element (96) can influence the operation of another processing element (96) only as set forth by the separation specification (99). In particular, the separation specification provides memory allocation, remote procedure calls and exception handling mechanisms.

Abstract: A hardware resource manager (18) dynamically allocates hardware resources in a software-defined communications system. The hardware resource manager (18) creates a specification of required hardware resources (300) necessary for executing a system application. The hardware resource manager (18) then creates a list of candidate hardware resources (306) from the plurality of available hardware resources in response to an application creating its own abstract resource specification (78) of required hardware resources. The hardware resource manager (18) then maps each required hardware resource on the specification of required hardware resources to a least functional and most available candidate hardware resource on the list of candidate hardware resources in a manner that maximally preserves most functional and least available candidate hardware resources on the list of candidate hardware resources (316-326).

Abstract: A data security system (26) provides cryptographic services in a multiprocessor platform (20) supporting a distributed application (22). The distributed application (22) includes a cryptographic object (52) that is executable exclusively on the data security system (26). An input interface object (102), a cryptographic function (90), and an output interface objection (104) form the cryptographic object (52). The data security system (26) includes a first processor element (92) for executing the input interface object (102), a second processor element (94) for executing the cryptographic function (90), and a third processor element (96) for executing the output interface object (104). The combination of data security system (26) and cryptographic object (52) ensures the separation of plain text data (46) from cipher text data (48).

Abstract: A voltage-controlled oscillator in which a tunable resonator (102) having a first port (132) and a second port (106) is disclosed. In one embodiment, the tunable resonator is a series resonating circuit having low driving and load impedances. A power gain element (108) is coupled to the first port and the second port, and an output port (110) is coupled to the power gain element and the second port. The first impedance at the first and second ports is less than approximately ten ohms. The voltage-controlled oscillator is capable of generating a signal at the output port of greater than approximately half a watt.

Abstract: A communication system (20) employs fixed rate channel-optimized, trellis-coded quantization (COTCQ) at a plurality of diverse encoding bit rates. COTCQ is performed through a COTCQ encoder (40) and COTCQ decoder (54). The COTCQ encoder and decoder (40,54) each include a codebook table (62) having at least one codebook (64) for each encoding bit rate. Each codebook (64) is configured in response to the bit error probability of the channel (26) through which the communication system (20) communicates. The bit error probability influences codebooks through the calculation of channel transition probabilities for all combinations of codewords (90) receivable from the channel (26) given all combinations of codewords (90) transmittable through the channel (26). Channel transition probabilities are responsive to base channel transition probabilities and the hamming distances between indices for codewords within subsets of the transmittable and receivable codewords.