Abstract: A monitoring system for a HFC network includes a plurality of “test points” disposed at various locations throughout the network. Each test point is used to allow for the isolation of communication problems within the network (for example, ingress) and mitigation of the effects of the network problems. By distributing a plurality of test points throughout the topology of the network, only limited sections of the network need to be isolated at any point in time to address the particular communication problem.

Abstract: A system for overlaying digital character signals on an analog video source signal including a predetermined color subcarrier includes a subcarrier phase lock loop, a digital character generating device, a digital video encoder, and a switching device. The subcarrier phase lock loop separately generates a color subcarrier and a system clock signal which are locked to the color subcarrier of the analog video source signal. The digital character generating device detects horizontal and vertical timing of pixel information in the analog video source signal, and generates digital character signals that are to be overlaid in predetermined pixels of the analog video source signal. The digital video encoder is responsive to the color subcarrier and system clock signals for generating a separate color subcarrier which is locked to the color subcarrier of the analog video source signal.

Abstract: An oscillator system and method in which a time period (inverse of frequency) of a multi-stage ring oscillator (ROSC) is adjusted by a bias current which controls the charging and discharging times of respective capacitors (e.g., interelectrode capacities) within each stage. The time periods of the unadjusted oscillator are counted along with the time periods of a reference clock over a same period of time and a count difference between the two counts is determined. The count difference is applied by a logic circuit in accordance with an algorithm relating count differences to incremental bias current levels to adjust the frequency of the oscillator. The logic circuit generates digital gate signals corresponding to the count difference and these signals automatically select the bias current level needed to bring the oscillator frequency into close agreement with the reference clock frequency.