Abstract: A method in a signal processor for filtering samples in a digital signal is provided. An approximate filtered sample is generated as a function of less than four samples of the digital signal. A correction is generated as a function of the less than four samples, and a filtered sample is generated by modifying the approximate filtered sample with the correction.

Abstract: The generation and upstream transmission of voice packets in an HFC network is controlled by including a synchronization circuit in the broadband terminal interface unit. The synchronization circuit is used to generate the timing signals for the codec, DSP and host microprocessor so that as the host microprocessor receives an upstream grant, the remaining components will assemble and forward the packets in synchronization with the grant.

Abstract: A composite video multiplexing arrangement for allowing a plurality of low bit rate video signals to be multiplexed into a single coded signal to be transmitted to an associated receiver. For use with arrangements such a security system, each video “source” (such as a camera) includes a coder module for forming a digital representation of the video, including both “source” and “line” information. Each coder module includes a FIFO buffer for holding this data until multiplexed onto the single output signal. An associated decoder is capable of extracting the “source” and “line” information and regenerating each separate video signal.

Abstract: The capacity and realized data rate of a data storage medium is increased by storing multiple bits per symbol using digital modulation techniques. Both phase and amplitude modulation techniques can be applied so that each symbol includes two or more bits that are represented by in-phase and quadrature phase portions of the signal corresponding to the data on the medium.

Abstract: According to the invention, a content processing unit for protecting interchip content pathways transporting digital content objects is disclosed. The content processing unit includes a first chip package, a second chip package and a content pathway. The first chip package includes a first body, a first plurality of interconnects, an encryption engine, and a first key storage register capable of storing a first key, and the second chip package includes a second body, a second plurality of interconnects, an encryption engine, and a second key storage register capable of storing a second key. The first key is used by the encryption engine to produce ciphertext content and cannot be overwritten after a programmability period. The first and second key storage registers are non-readable from outside the first body. The second key is used by the decryption engine to produce plaintext content from the ciphertext content.

Abstract: According to the invention, a method for protecting digital television from unauthorized digital receivers within a population of digital receivers is disclosed. Each digital receiver in the population has a unique identifier. In one step, provisioning information is received from a subset of the population of digital receivers indicating that the subset is potentially within range to receive digital television from a broadcaster. First decryption information is distributed to the subset of the population of digital receivers. The first decryption information allows for potentially decrypting a plurality of programs coextensively in time. The unauthorized digital receivers are cryptographically excluded from using the first decryption information. A first program is encrypted using a first method that is cryptographically related to second decryption information. The first program is sent. The second decryption information is distributed and cryptographically secured with the first decryption information.

Abstract: According to the invention, a circuit that is capable of automated scan testing is disclosed. Included in the circuit are a cryptographic engine, a digital circuit, an input pin, and an output pin. The cryptographic engine capable of performing at least one of encryption and decryption of one or more digital signals. The digital circuit includes combinatorial logic and a number of memory cells. The memory cells have scan inputs connected serially in a scan chain. The input pin and output pin are coupled to the scan chain. At least one of the input pin and the output pin carries at least some cipher text data of the scan chain.

Abstract: A guide member for accommodating a removable module is formed from a thermally conductive material having at least one thermally conductive element to provide a new primary heat dissipation path to manage thermal energy generated by operation of the module. The guide member may also be used to guide the module into proper connection with a module connector which electrically connects the circuit on the module with other circuitry. A plurality of thermally conductive elements, such as spring fingers, ribs and fins, provide additional thermal heat dissipation paths and enhance the rigidity of the guide members.

Abstract: An upconverter for converting IF television signals to VHF or UHF signals prior to broadcast is configured to process either analog or digital television signals. The upconverter identifies the type of incoming television signal and generates an appropriate reference signal depending on whether the incoming television signal is digital or analog. In an analog format, the reference signal is used by the modulator generating the IF signal to synchronize phase with the signals output by various other upconverters. In a digital format, the reference signal is used, for example, as a test signal for the upconversion circuit.

Abstract: An improved electronic device, for example, an upconverter for converting an IF television signal to a VHF or UHF television signal at a broadcast signal headend provides an external, shielded bus interface which connects to filtered internal input and output lines leading to control circuitry. The resulting device suppresses unwanted electromagnetic emissions.

Abstract: An improved electronic device, for example, an upconverter for converting an IF television signal to a VHF or UHF television signal at a broadcast signal headend provides an external, shielded bus interface which connects to filtered internal input and output lines leading to control circuitry. The resulting device suppresses unwanted electromagnetic emissions.

Abstract: A semiconductor device comprises a monocrystalline silicon wafer having a major surface lying in the {100} crystal plane. Disposed on the surface is a mesa having a generally square cross-section with generally rounded corners. The mesa has four main side walls each having a slope of around 45 degrees with respect to the base plane of the mesa, and the horizontal edges of the main side walls are disposed at an angle of at least around 12 degrees to the {111} directions on the wafer surface. The corners of the mesa each comprises a number of surfaces also having slopes of around 45 degrees and one surface having a slope of around 54 degrees. A high-low (N.sup.+ N.sup.- or P.sup.+ P.sup.-) junction is disposed within the mesa and makes a continuous line intercept with the mesa side walls around the entire periphery of the mesa. Except for exceptionally small deviations of no great significance, the high-low junction intercept is at a constant height location entirely around the mesa periphery.

Abstract: A pair of metal lead frames are stacked together with a plurality of solder coated semiconductor chips sandwiched between respective pairs of overlapped portions of the lead frames and the lead frame stack is then disposed within a fixture comprising spaced apart clamping means for clamping together the overlapped portions of the lead frames. Only the clamping means contact the frame stack and in thermally and electrically insulated relation therewith for minimizing heat loss from and electrical shorting of the lead frame stack to the fixture. Electrodes are tightly clamped against exposed ends of the lead stack for passing electrical current through the stack for causing electrical resistance heating of the stack and the soldering of the chips to the lead frames.

Abstract: A distributed antenna PCN system provides for telephone service on a CATV network. The PCN antenna signal from one PCN node is transported to more than one remotely located antenna nodes via the cable. Thus, rather than having a PCN cell shape equal to the radiation pattern of one antenna node, a distributed antenna system creates a cell shape having a distributed pattern, equal to the sum of the radiation patterns of the individual antenna nodes. A single PCN cell is then not necessarily a contiguous area but may include a number of geographically separated areas so that subscriber locations which are not physically adjacent may be included in the same cell. Therefore, the CATV operator may offer universal service to all subscribers in the CATV system using a first PCN node and add subscribers to the first PCN node as needed, regardless of subscriber location.

Abstract: Semiconductor rectifier devices having oppositely extending terminals lying in a common plane are fabricated using upper and lower lead frames each comprising a pair of parallel side rails and spaced apart cross bars extending between the side rails. Cantilevered terminals are mounted along the cross bars. The cross bars of the upper frame lie in a plane downwardly off-set from the plane of the upper frame, and the cross bars of the lower frame lie in a plane upwardly off-set from the plane of the lower frame. Free ends of the terminals of the upper frame lie in a plane upwardly off-set from the plane of the upper frame cross bars, and free ends of the terminals of the lower frame are off-set downwardly from the plane of the lower frame cross bars. Semiconductor chips are mounted on the terminal free ends of the lower frame, and the upper frame is disposed on top of the lower frame with the upper frame terminals contacting the chips.

Abstract: Circuits embodying the invention include means for sensing certain characteristics (e.g. speed of response and conductivity) of the transistors formed on an integrated circuit (IC) and for using the sensed results to control the operation and structure of a circuit formed on the IC. An output driver circuit embodying the invention includes numerous pull-up transistors connected in parallel between a high power supply line and an output terminal and numerous pull-down transistors connected in parallel between the output terminal and the low power supply line. The number of transistors which are turned-on at any one time is selectively controlled as a function of the characteristics (e.g. conductivity and speed of response) of the transistors of the circuit. The higher the speed of response or the conductivity of the transistors, the fewer the number of pull-up or pull-down transistors which are turned-on.

Abstract: A memory system includes a memory array of cells arranged in "r" rows and "c" columns, with each row of cells connected to a write conductor and to a separate read conductor. The memory array may be simultaneously written into and read from by a write address decoder having "r" outputs, one output connected to and corresponding to each write conductor and a read address decoder having "r" outputs, one output connected to and corresponding to each read conductor. Control signals are applied to the write address decoder to cause the outputs of the write address decoder to scan the memory array at a first rate, in sequence, in a first direction, and control signals are applied to the read address decoder to cause the outputs of the read address decoder to scan the memory array at a second rate, in sequence, in a second direction, opposite the first direction.

Abstract: Semiconductor rectifier devices having oppositely extending terminals lying in a common plane are fabricated using upper and lower lead frames each comprising a pair of parallel side rails and spaced apart cross bars extending between the side rails. Cantilevered terminals are mounted along the cross bars. The cross bars of the upper frame lie in a plane downwardly off-set from the plane of the upper frame, and the cross bars of the lower frame lie in a plane upwardly off-set from the plane of the lower frame. Free ends of the terminals of the upper frame lie in a plane upwardly off-set from the plane of the upper frame cross bars, and free ends of the terminals of the lower frame are off-set downwardly from the plane of the lower frame cross bars. Semiconductor chips are mounted on the terminal free ends of the lower frame, and the upper frame is disposed on top of the lower frame with the upper frame terminals contacting the chips.

Abstract: Two phase bridge rectifiers are fabricated starting with three lead flames and bonding a first pair of semiconductor chips on mounting pads of a first of the frames and a second pair of semiconductor chips on mounting pads of a second of the frames. The frames are then disposed one on top of the other with upper surfaces of the first pair of chips contacting under surfaces of the mounting pads of the second frame and with upper surfaces of the second pair of chips contacting under surfaces of a pair of mounting pads on the third frame. A mounting pad on the third (upper) frame includes an extension thereof extending downwardly and bonded to a terminal formed in the second (middle) frame, and a mounting pad on the first (lower) frame includes an extension thereof extending upwardly and bonded to another terminal of the second frame.

Abstract: A semiconductor rectifier device includes a mesa structure formed on a surface of a monocrystalline silicon wafer, the mesa having four side walls meeting at rounded corner walls. The slope of the mesa side walls is 45 degrees and the slope of each corner wall varies between 45 and 54 degrees. The mesa is fabricated by providing a square etchant mask having rounded corners on a <100> crystal plane of a silicon wafer with the straight sides of the mask disposed at an angle of 45 degrees with <111> directions on the wafer surface. The mask corners are symmetrical and comprise, from a mid point of the corners, oppositely extending short straight lines forming an angle of 150 degrees or less therebetween. The rear end of each short line is connected by a series of end to end straight lines angled relative to one another to form a generally smooth line merging with straight sides of the mask.