Abstract: An upconverter for converting IF television signals to VHF or UHF signals prior to broadcast is configured to process either analog or digital television signals. The upconverter identifies the type of incoming television signal and generates an appropriate reference signal depending on whether the incoming television signal is digital or analog. In an analog format, the reference signal is used by the modulator generating the IF signal to synchronize phase with the signals output by various other upconverters. In a digital format, the reference signal is used, for example, as a test signal for the upconversion circuit.

Abstract: An improved electronic device, for example, an upconverter for converting an IF television signal to a VHF or UHF television signal at a broadcast signal headend provides an external, shielded bus interface which connects to filtered internal input and output lines leading to control circuitry. The resulting device suppresses unwanted electromagnetic emissions.

Abstract: Circuits embodying the invention include means for sensing certain characteristics (e.g. speed of response and conductivity) of the transistors formed on an integrated circuit (IC) and for using the sensed results to control the operation and structure of a circuit formed on the IC. An output driver circuit embodying the invention includes numerous pull-up transistors connected in parallel between a high power supply line and an output terminal and numerous pull-down transistors connected in parallel between the output terminal and the low power supply line. The number of transistors which are turned-on at any one time is selectively controlled as a function of the characteristics (e.g. conductivity and speed of response) of the transistors of the circuit. The higher the speed of response or the conductivity of the transistors, the fewer the number of pull-up or pull-down transistors which are turned-on.

Abstract: A memory system includes a memory array of cells arranged in "r" rows and "c" columns, with each row of cells connected to a write conductor and to a separate read conductor. The memory array may be simultaneously written into and read from by a write address decoder having "r" outputs, one output connected to and corresponding to each write conductor and a read address decoder having "r" outputs, one output connected to and corresponding to each read conductor. Control signals are applied to the write address decoder to cause the outputs of the write address decoder to scan the memory array at a first rate, in sequence, in a first direction, and control signals are applied to the read address decoder to cause the outputs of the read address decoder to scan the memory array at a second rate, in sequence, in a second direction, opposite the first direction.