Abstract: A frequency scanning receiver minimizes the time needed for setting the frequency of a phased lock loop of a first local oscillator. The frequency scanning receiver is configured so that when the reference frequency of the PLL of the first local oscillator has been set at a high frequency, and the frequency error is less than the second IF, the frequency error is controlled to be zero by the control circuit switching the frequency of a second local oscillator or third local oscillator to an appropriate frequency using an output of a frequency discriminator.

Abstract: Selectivity Q of a tuning circuit is maximized by using a negative resistance circuit that is not influenced significantly by changes in conditions such as temperature, source voltage, etc. The tuning circuit operates stably and is constituted by a series resonance circuit and the negative resistance circuit connected thereto. The negative resistance circuit can be a C-E dividing type circuit including a npn transistor as a first stage circuit and an emitter earth type amplifying circuit including a pnp transistor as a second stage circuit. A collector output of the pnp transistor is connected to an emitter of the npn transistor to constitute a negative feedback circuit and the collector output is divided and connected to a base of the npn transistor to constitute a positive feedback circuit. Selectivity Q is improved by the negative resistance circuit provided by the negative feedback circuit.

Abstract: A circuit for detecting and correcting a center level is constituted for when the length of a code of “1” or “0” in an FSK signal is extremely long and superimposed with a frequency fluctuation of a transmitter/receiver. This circuit has sample value holding circuits exclusive to “1” and “0” of an input demodulation data signal. After a difference voltage between both sample values is once converted to a digital code in an ADA converter, the converted code is re-converted to an analog value, thereby holding the value digitally. When “1” s repeat, the hold voltage to “1” is updated to new values and simultaneously a voltage obtained by subtracting the difference voltage from the above-described voltage is applied to the holding circuit for “0” to update the value in the holding circuit. Also, when “0”s repeat, the processing proceeds in reverse and the holding circuit for “1” is updated with a voltage obtained by adding the difference voltage to the hold voltage.

Abstract: A tuning circuit using a negative resistance circuit for compensating an equivalent series resistance component thereof is provided. The negative resistance circuit has simple circuit construction and design and adjustment thereof is easy. The tuning circuit comprises a series resonance circuit and a negative resistance circuit connected to the series resonance circuit in series. In the negative resistance circuit, a first transistor constitutes an inverse amplifier by providing a resistor in an emitter circuit thereof and a second transistor constitutes an emitter follower circuit. A positive feedback circuit is constituted by feeding back an output of the emitter follower circuit to an emitter circuit of the first transistor and a negative feedback circuit is constituted by feeding back an output terminal to a base circuit of the first transistor. Thus a negative resistance is produced between this base input terminal and an earth.

Abstract: In order to improve Q of a tuning circuit by using a negative resistance circuit, a tuning circuit wherein a frequency selectivity characteristic and a tuning circuit gain does not vary and are kept constant values even if a tuning frequency is changed, is provided. The tuning circuit is constructed so as to compensate a series resistance component by connecting a negative resistance circuit to a series resonance circuit. The negative resistance circuit includes a differential amplifying circuit having two transistors emitters of which are connected in common, and a low output impedance circuit such as an emitter follower. The low impedance output is fed back to a same phase input side of the differential amplifying circuit directly and also to an inverse phase input side thereof to obtain a negative resistance value at this inverse input terminal.

Abstract: An all pass filter capable of adjusting a center frequency and Q independently from one another, even in a high frequency band. In the filter, an input signal from an input terminal is applied to a gain control circuit and a subtraction circuit, and after a gain of an output signal of a tuning circuit is adjusted by a resistor dividing circuit, it is amplified by a first transistor in phase. An input signal not passing through the tuning circuit is amplified inversely by a second transistor. Since the transistors are connected to a common load resistor, the input signal and the output signal of the tuning circuit are subtracted and a difference voltage therebetween appears at the load resistor.

Abstract: A low pass notch filter has a notch frequency close to &ohgr;o. In the notch filter, an output of an operational amplifier is fed back to an inverting input terminal thereof through a second voltage dividing circuit and a charge/discharge resistor. A first voltage dividing circuit is connected between a signal input terminal and a capacitor which is connected to the inverting input terminal. A signal from the output of the operational amplifier to the second voltage dividing circuit is fed back to a divided output point of the first voltage dividing circuit through a capacitor. At the same time, the signal input terminal provides a signal to the non-inverting input terminal of the operational amplifier through a third voltage dividing circuit.

Abstract: A character input method enables mistake of character input to be diminished, and it is unnecessary to use a rotary type switch in the character input method, therefore it is economical. In a frequency scanning type receiver, when it causes character input to be performed according to a key board section, respective numeric-keys 1 to 0 of 10-key correspond to a plurality of character groups consisting of capital letter, small letter of an alphabet, and numerals arranged in accordance with prescribed order to be determined. CPU/memory section selects the corresponding character group according to a numeric-key which is pressed firstly, next, the CPU/memory section selects corresponding alphabet character, numeral from among character group according to numeric-key which is pressed secondly.

Abstract: A tuning circuit is constructed to set Q of the tuning circuit to a high desired value by using a negative resistance value. The tuning circuit is made to oscillate weakly by using a negative resistance circuit, a voltage-resistance converter and a digital-analog converter. A negative resistance of the negative resistance circuit is scanned by a counter so that two negative resistance values corresponding to an oscillation amplitude and another oscillation amplitude of one half are obtained by analog comparators COMP1 and COMP2. A negative resistance value to be set is operated by an adder/subtracter from a series resistance value corresponding to a desired Q and this value. Scanning is stopped when the negative resistance value is obtained. The tuning circuit can be formed by small size digital integrated circuits.

Abstract: A frequency scanning receiver for a FSK signal of such a type that a center frequency is provided in an overhead portion of a packet. The receiver is constructed so that a remaining center level error, when the FSK signal is found by frequency scanning of a local oscillator, can be set to substantially zero even when frequency scanning is done quickly. In the receiver, a conversion point detector detects a time point when a demodulated base band signal having a center frequency output from a center frequency detector is scanned by a VFO and then crosses over a zero point in a comparator. At the time point a scanning voltage is held and is corrected by a correcting voltage from a correcting signal generating circuit, whereby an overpassing quantity corresponding to a scanning speed and a loop delay time of a system of the receiver can be corrected.

Abstract: A direct modulating frequency shift keying transmitter for multi channel access is constructed so that a transmission signal from a voltage controlled oscillator (VCO) in a phase lock loop frequency synthesizer is output through a buffer amplifier and a transmitting power amplifier, and a modulation signal is applied to the VCO. In the transmitter, in order to cancel instantaneous deviation of a transmission frequency due to ON of the transmitting power amplifier, an ON/OFF control signal is applied to the transmitting power amplifier.

Abstract: A tuning circuit has a simple circuit construction and is capable of setting Q thereof to a high desired value. The tuning circuit is formed by a resonance circuit consisting of an inductor and a capacitor and a negative resistance circuit connected in series to the resonance circuit including a negative impedance converter and a variable resistor. A counter counts clock signals from a clock signal generating circuit and a count value is converted to an analog signal by a D/A converter. The negative resistance circuit is controlled by the analog signal so that an effective resistance of the tuning circuit is made negative to oscillate and to vary a negative resistance value in a positive direction. When the effective resistance value becomes zero, oscillation stops and thereafter when a value of Q becomes a predetermined value, the clock signals are stopped and the latch circuit holds a final count value.

Abstract: An each area automatic selection receiver of an emergency radio signal is an emergency broadcast receiver which enables current area code CAC to be updated automatically. This receiver is constituted in such a way that a GPS receiver obtains current position information by use of the satellite positioning system, then, a converter converts the current position information into an area code by use of a conversion table to write the area code into a code memory. For that reason, even though the receiver moves anywhere, contents of the code memory are always updated to an area code of an area of the movement destination automatically. Therefore, emergency broadcast of the area is always capable of being received correctly.

Abstract: Since in a demodulated base band signal in an FSK receiver, etc. usually a DC offset is produced due to a frequency difference between a transmitter and a receiver, etc., which lowers demodulation margin, a circuit is constructed for detecting an error in a center level thereof to correct same in a simple manner. In this circuit, a bit synchronizing signal, which is at a beginning of a the base band signal EB is sampled twice with an interval of 1/(baud rate) sec and an average of two sampled values is obtained by applying sampled output pulses thus obtained to a holding capacitor in a hold circuit. In this way the error in the center level is detected and the center level is corrected by subtracting it from the base band signal in a subtracter.

Abstract: In order to automatically set a Q value to an optimal value, a tuning circuit has a resonance circuit composed of an inductor and a capacitor. The resonance circuit includes a negative resistance circuit having a dummy load resistance and a negative impedance converter. An operating circuit provides the dummy load resistance so that a negative resistance value is output to obtain a desired Q value.

Abstract: A FSK signal demodulating integration-discharge circuit has a simple circuit configuration and utilizes an AC waveform of the FSK signal as a. control signal for a transistor gate. FSK signals are converted into rectangular-wave signals by the use of a limiter, before adding the rectangular-wave signal to an integrating capacitor C1 through a resistor. The capacitor C1 connects to a first transistor in parallel thereto, which is turned ON/OFF due to the rectangular-wave signal. The signal causes the capacitor C1 to be charged by the voltage corresponding to time length of a half cycle of a portion of positive voltage of the rectangular-wave signal, while causing the above capacitor C1 to discharge in terms of electric charge of the capacitor C1 by the voltage corresponding to time length of a half cycle of a portion of negative voltage of the rectangular-wave signal. Charged voltage from the capacitor C1 also feeds into a holding capacitor C2 through a second transistor.

Abstract: A tuning circuit enables its Q to be always maintained with the condition of high grade even when tuning frequency of the tuning circuit is changed. The tuning circuit is constituted in such a way that a negative resistance circuit is connected to the tuning circuit in series. Series resistance component of an inductor of the tuning circuit is divided into a fixed resistance component r0 having nothing to do with a frequency and a variable resistance component r1 which is changed depending on a frequency. Load resistances r0′, and r1′ of the negative resistance circuit are made to correspond to the fixed resistance component r0 and the variable resistance component r1 respectively. When changing the tuning frequency, operation is made to control in such a way that the load resistance r1′ of the negative resistance circuit which corresponds to the variable resistance component r1 is changed while corresponding to change of actual resistance value of the tuning circuit.

Abstract: In a frequency scanning receiver for a packet FSK signal of such a type that a duration to issue a center frequency is provided in head portion thereof, the packet FSK signal is scanned by a scanning voltage from VFO in a frequency converter to provide an IF signal which is applied to a frequency detector to provide a demodulated base band signal. The demodulated base band signal is applied to a comparator to compare it with a reference signal and a conversion point detector detects inversion of an output signal of the comparator. A sample and hold circuit holds a sample value of the scanning voltage when the inversion is detected until end of a packet to keep a center frequency error in a minimum condition.