Patents Assigned to General Semiconductor, Inc.
  • Patent number: 8513732
    Abstract: A power MOSFET is provided that includes a substrate of a first conductivity type. An epitaxial layer also of the first conductivity type is deposited on the substrate. First and second body regions are located in the epitaxial layer and define a drift region between them. The body regions have a second conductivity type. First and second source regions of the first conductivity type are respectively located in the first and second body regions. A plurality of trenches are located below the body regions in the drift region of the epitaxial layer. The trenches, which extend toward the substrate from the first and second body regions, are filled with a material that includes a dopant of the second conductivity type. The dopant is diffused from the trenches into portions of the epitaxial layer adjacent the trenches.
    Type: Grant
    Filed: January 30, 2006
    Date of Patent: August 20, 2013
    Assignee: General Semiconductor, Inc.
    Inventor: Richard A. Blanchard
  • Patent number: 8130006
    Abstract: An electronic element testing apparatus for use with a number of probes. Each probe has a lower pole and an upper pole. The apparatus includes: a first plate having a first side and a second side, the first side having an array of lower pole regions disposed thereabout, each lower pole region configured to receive a lower pole of a probe; and a plurality of signal conductor regions disposed proximate the array of lower pole regions, each signal conductor region arranged to provide a non-cable electrical path between a lower pole region and a switching circuit. The switching circuits are operable to sequentially connect each electronic element to a testing circuit via the upper and lower poles.
    Type: Grant
    Filed: January 12, 2010
    Date of Patent: March 6, 2012
    Assignee: Vishay General Semiconductor, inc.
    Inventors: Kuang-Jung Li, Chin-Chen Hsu, Yi-Li Lin, Shyan-I Wu
  • Patent number: 7768104
    Abstract: An apparatus and method for a two semiconductor device package where the semiconductor devices are connected in electrical series. The first device is mounted P-side down on an electrically conductive substrate. Non-active area on the P side is isolated from the electrically conductive substrate. The second device is mounted P-side up at a spaced apart location on the substrate. Opposite sides of each are electrically connected to leads to complete the series connection of the two devices. A method of manufacturing such a package includes providing an electrically conductive lead frame, mounting one device P-side up and flipping the other device and mounting it P-side down on the lead frame with non-active area of the P side isolated from the lead frame, and connecting the other side of each device to separate leads. Isolation of the non-active area of the P side of the device can be through modification of the substrate or lead frame surface by grooves or raised portions.
    Type: Grant
    Filed: March 18, 2008
    Date of Patent: August 3, 2010
    Assignee: Vishay General Semiconductor, Inc.
    Inventors: Ta-Te Chou, Hui-Ying Ding, Yun Zhang, Hong-Yun He, Li-Zhu Hao
  • Patent number: 7745885
    Abstract: A power MOSFET is provided that includes a substrate of a first conductivity type. An epitaxial layer also of the first conductivity type is deposited on the substrate. First and second body regions are located in the epitaxial layer and define a drift region between them. The body regions have a second conductivity type. First and second source regions of the first conductivity type are respectively located in the first and second body regions. A plurality of trenches are located below the body regions in the drift region of the epitaxial layer. The trenches, which extend toward the substrate from the first and second body regions, are filled with an epitaxially layered material that includes a dopant of the second conductivity type. The dopant is diffused from the trenches into portions of the epitaxial layer adjacent the trenches.
    Type: Grant
    Filed: June 27, 2006
    Date of Patent: June 29, 2010
    Assignee: General Semiconductor, Inc.
    Inventor: Richard A. Blanchard
  • Publication number: 20100109692
    Abstract: An electronic element testing apparatus for use with a number of probes. Each probe has a lower pole and an upper pole. The apparatus includes: a first plate having a first side and a second side, the first side having an array of lower pole regions disposed thereabout, each lower pole region configured to receive a lower pole of a probe; and a plurality of signal conductor regions disposed proximate the array of lower pole regions, each signal conductor region arranged to provide a non-cable electrical path between a lower pole region and a switching circuit. The switching circuits are operable to sequentially connect each electronic element to a testing circuit via the upper and lower poles.
    Type: Application
    Filed: January 12, 2010
    Publication date: May 6, 2010
    Applicant: VISHAY GENERAL SEMICONDUCTOR, INC.
    Inventors: Kuang-Jung LI, Chin-Chen HSU, Yi-Li Lin, Shyan-I Wu
  • Publication number: 20090236705
    Abstract: An apparatus and method for a two semiconductor device package where the semiconductor devices are connected in electrical series. The first device is mounted P-side down on an electrically conductive substrate. Non-active area on the P side is isolated from the electrically conductive substrate. The second device is mounted P-side up at a spaced apart location on the substrate. Opposite sides of each are electrically connected to leads to complete the series connection of the two devices. A method of manufacturing such a package includes providing an electrically conductive lead frame, mounting one device P-side up and flipping the other device and mounting it P-side down on the lead frame with non-active area of the P side isolated from the lead frame, and connecting the other side of each device to separate leads. Isolation of the non-active area of the P side of the device can be through modification of the substrate or lead frame surface by grooves or raised portions.
    Type: Application
    Filed: March 18, 2008
    Publication date: September 24, 2009
    Applicant: VISHAY GENERAL SEMICONDUCTOR, INC.
    Inventors: TA-TE CHOU, HUI-YING DING, YUN ZHANG, HONG-YUN HE, LI-ZHU HAO
  • Patent number: 7586148
    Abstract: A method is provided for forming a power semiconductor device. The method begins by providing a substrate of a first conductivity type and forming a voltage sustaining region on the substrate. The voltage sustaining region is formed in the following manner. First, an epitaxial layer is deposited on the substrate. The epitaxial layer has a first or a second conductivity type. Next, at least one terraced trench is formed in the epitaxial layer. The terraced trench has a trench bottom and a plurality of portions that differ in width to define at least one annular ledge therebetween. A barrier material is deposited along the walls and bottom of the trench. A dopant of a conductivity type opposite to the conductivity type of the epitaxial layer is implanted through the barrier material lining the annular ledge and at the trench bottom and into adjacent portions of the epitaxial layer to respectively form at least one annular doped region and another doped region.
    Type: Grant
    Filed: July 31, 2006
    Date of Patent: September 8, 2009
    Assignee: General Semiconductor, Inc.
    Inventor: Richard A. Blanchard
  • Patent number: 7525183
    Abstract: A surface mountable multi-chip device is provided which includes first and second lead frames portions and at least two chips. The lead frame portions each include a header region and a lead region. Beneficially, the header regions of the first and second lead frame portions lie in a common plane, with at least one semiconductor chip being placed on each of the header regions. A conductive member link is placed on top of the two chips to electrically and mechanically interconnect the chips.
    Type: Grant
    Filed: July 10, 2007
    Date of Patent: April 28, 2009
    Assignee: General Semiconductor, Inc.
    Inventors: Paddy O'Shea, Eamonn Medley, Finbarr O'Donoghue, Gary Horsman
  • Publication number: 20080136431
    Abstract: An electronic element testing apparatus for use with a number of probes. Each probe has a lower pole and an upper pole. The apparatus includes: a first plate having a first side and a second side, the first side having an array of lower pole regions disposed thereabout, each lower pole region configured to receive a lower pole of a probe; and a plurality of signal conductor regions disposed proximate the array of lower pole regions, each signal conductor region arranged to provide a non-cable electrical path between a lower pole region and a switching circuit. The switching circuits are operable to sequentially connect each electronic element to a testing circuit via the upper and lower poles.
    Type: Application
    Filed: February 13, 2008
    Publication date: June 12, 2008
    Applicant: Vishay General Semiconductor, Inc.
    Inventors: Kuang-Jung Li, Chin-Chen Hsu, Yi-Li Lin, Shyan-l Wu
  • Patent number: 7374293
    Abstract: An electronic element testing apparatus for use with a number of probes. Each probe has a lower pole and an upper pole. The apparatus includes: a first plate having a first side and a second side, the first side having an array of lower pole regions disposed thereabout, each lower pole region configured to receive a lower pole of a probe; and a plurality of signal conductor regions disposed proximate the array of lower pole regions, each signal conductor region arranged to provide a non-cable electrical path between a lower pole region and a switching circuit. The switching circuits are operable to sequentially connect each electronic element to a testing circuit via the upper and lower poles.
    Type: Grant
    Filed: March 25, 2005
    Date of Patent: May 20, 2008
    Assignee: Vishay General Semiconductor Inc.
    Inventors: Kuang-Jung Li, Chin-Chen Hsu, Yi-Li Lin, Shyan-I Wu
  • Patent number: 7304347
    Abstract: A method is provided for forming a power semiconductor device. The method begins by providing a substrate of a first conductivity type and then forming a voltage sustaining region on the substrate. The voltage sustaining region is formed by depositing an epitaxial layer of a first conductivity type on the substrate and forming at least one terraced trench in the epitaxial layer. The terraced trench has a plurality of portions that differ in width to define at least one annular ledge therebetween. A barrier material is deposited along the walls of the trench. A dopant of a second conductivity type is implanted through the barrier material lining the annular ledge and said trench bottom and into adjacent portions of the epitaxial layer. The dopant is diffused to form at least one annular doped region in the epitaxial layer and at least one other region located below the annular doped region.
    Type: Grant
    Filed: November 13, 2003
    Date of Patent: December 4, 2007
    Assignee: Vishay General Semiconductor Inc.
    Inventors: Richard A. Blanchard, Jean-Michel Guillot
  • Patent number: 7242078
    Abstract: A surface mountable multi-chip device is provided which includes first and second lead frames portions and at least two chips. The lead frame portions each include a header region and a lead region. Beneficially, the header regions of the first and second lead frame portions lie in a common plane, with at least one semiconductor chip being placed on each of the header regions. A conductive member link is placed on top of the two chips to electrically and mechanically interconnect the chips.
    Type: Grant
    Filed: July 18, 2005
    Date of Patent: July 10, 2007
    Assignee: General Semiconductor, Inc.
    Inventors: Paddy O'Shea, Eamonn Medley, Finbarr O'Donoghue, Gary Horsman
  • Patent number: 7224027
    Abstract: A method is provided for forming a power semiconductor device. The method begins by providing a substrate of a first or second conductivity type and then forming a voltage sustaining region on the substrate. The voltage sustaining region is formed by depositing an epitaxial layer of a first conductivity type on the substrate and forming at least one trench in the epitaxial layer. A first layer of polysilicon having a second dopant of the second conductivity type is deposited in the trench. The second dopant is diffused to form a doped epitaxial region adjacent to the trench and in the epitaxial layer. A second layer of polysilicon having a first dopant of the first conductivity type is subsequently deposited in the trench. The first and second dopants respectively located in the second and first layers of polysilicon are interdiffused to achieve electrical compensation in the first and second layers of polysilicon.
    Type: Grant
    Filed: September 20, 2004
    Date of Patent: May 29, 2007
    Assignee: General Semiconductor, Inc.
    Inventor: Richard A. Blanchard
  • Patent number: 7199427
    Abstract: A DMOS device is provided which is equipped with a floating gate having a first and second electrode in close proximity thereto. The floating gate is separated from one of the first and second electrodes by a thin layer of dielectric material whose dimensions and composition permit charge carriers to tunnel through the dielectric layer either to or from the floating gate. This tunneling phenomenon can be used to create a threshold voltage that may be adjusted to provide a precise current by placing a voltage between a programming electrode and the body/source and gate electrode of the device.
    Type: Grant
    Filed: April 12, 2005
    Date of Patent: April 3, 2007
    Assignee: General Semiconductor, Inc.
    Inventor: Richard A. Blanchard
  • Patent number: 7094640
    Abstract: A method of forming a trench MOSFET device includes depositing an epitaxial layer over a substrate, both having the first conductivity type, the epitaxial layer having a lower majority carrier concentration than the substrate, forming a body region of a second conductivity type within an upper portion of the epitaxial layer, etching a trench extending into the epitaxial layer from an upper surface of the epitaxial layer, the trench extending to a greater depth from the upper surface of the epitaxial layer than the body region, forming a doped region of the first conductivity type between a bottom portion of the trench and substrate, the doped region having a majority carrier concentration that is lower than that of the substrate and higher than that of the epitaxial layer, wherein the doped region is diffused and spans 100% of the distance from the trench bottom portion to the substrate, forming an insulating layer lining at least a portion of the trench, forming a conductive region within the trench adjacent
    Type: Grant
    Filed: December 1, 2003
    Date of Patent: August 22, 2006
    Assignee: General Semiconductor, Inc.
    Inventors: Fwu-Iuan Hshieh, Koon Chong So, John E. Amato, Yan Man Tsui
  • Patent number: 7091552
    Abstract: A power semiconductor device is made in accordance with a method of providing a substrate of a first or second conductivity type and then forming a voltage sustaining region on the substrate. The voltage sustaining region is formed by depositing an epitaxial layer of a first conductivity type on the substrate and forming at least one trench in the epitaxial layer. A barrier material is deposited along the walls of the trench. A dopant of a second conductivity type is implanted through the barrier material into a portion of the epitaxial layer adjacent to and beneath the bottom of the trench. The dopant is diffused to form a first doped layer in the epitaxial layer and the barrier material is removed from at least the bottom of the trench. The trench is etched through the first doped layer. A second doped layer is formed in the same manner as the first doped layer. The second doped layer is located vertically below the first doped layer.
    Type: Grant
    Filed: December 1, 2003
    Date of Patent: August 15, 2006
    Assignee: General Semiconductor, Inc.
    Inventor: Richard A. Blanchard
  • Patent number: 7084455
    Abstract: A method is provided for forming a power semiconductor device. The method begins by providing a substrate of a first conductivity type and forming a voltage sustaining region on the substrate. The voltage sustaining region is formed in the following manner. First, an epitaxial layer is deposited on the substrate. The epitaxial layer has a first or a second conductivity type. Next, at least one terraced trench is formed in the epitaxial layer. The terraced trench has a trench bottom and a plurality of portions that differ in width to define at least one annular ledge therebetween. A barrier material is deposited along the walls and bottom of the trench. A dopant of a conductivity type opposite to the conductivity type of the epitaxial layer is implanted through the barrier material lining the annular ledge and at the trench bottom and into adjacent portions of the epitaxial layer to respectively form at least one annular doped region and another doped region.
    Type: Grant
    Filed: February 2, 2004
    Date of Patent: August 1, 2006
    Assignee: General Semiconductor, Inc.
    Inventor: Richard A. Blanchard
  • Patent number: 7067376
    Abstract: A power MOSFET is provided that includes a substrate of a first conductivity type. An epitaxial layer also of the first conductivity type is deposited on the substrate. First and second body regions are located in the epitaxial layer and define a drift region between them. The body regions have a second conductivity type. First and second source regions of the first conductivity type are respectively located in the first and second body regions. A plurality of trenches are located below the body regions in the drift region of the epitaxial layer. The trenches, which extend toward the substrate from the first and second body regions, are filled with an epitaxially layered material that includes a dopant of the second conductivity type. The dopant is diffused from the trenches into portions of the epitaxial layer adjacent the trenches.
    Type: Grant
    Filed: September 29, 2003
    Date of Patent: June 27, 2006
    Assignee: General Semiconductor, Inc.
    Inventor: Richard A. Blanchard
  • Patent number: 7049194
    Abstract: A trench DMOS transistor device that comprises: (a) a substrate of a first conductivity type; (b) an epitaxial layer of first conductivity type over the substrate, wherein the epitaxial layer has a lower majority carrier concentration than the substrate; (c) a trench extending into the epitaxial layer from an upper surface of the epitaxial layer; (d) an insulating layer lining at least a portion of the trench; (e) a conductive region within the trench adjacent the insulating layer; (f) a body region of a second conductivity type provided within an upper portion of the epitaxial layer and adjacent the trench; (g) a source region of first conductivity type within an upper portion of the body region and adjacent the trench; and (h) one or more low resistivity deep regions extending into the device from an upper surface of the epitaxial layer. The low resistivity deep region acts to provide electrical contact with the substrate, which is a common drain region for the device.
    Type: Grant
    Filed: December 1, 2003
    Date of Patent: May 23, 2006
    Assignee: General Semiconductor, Inc.
    Inventors: Fwu-Iuan Hshieh, Koon Chong So, William John Nelson, John E. Amato
  • Patent number: 7019360
    Abstract: A method is provided for forming a power semiconductor device. The method begins by providing a substrate of a first conductivity type and then forming a voltage sustaining region on the substrate. The voltage sustaining region is formed by depositing an epitaxial layer of a first conductivity type on the substrate and forming at least one trench in the epitaxial layer. At least one doped column having a dopant of a second conductivity type is located in the epitaxial layer, adjacent a sidewall of the trench. The trench is etched using an etchant gas that also serves as a dopant source for the formation of the doped column. For example, if a p-type dopant such as boron is desired, BCl3 may be used as the etchant gas. Alternatively, if an n-type dopant such as phosphorus is required, PH3 may be used as the etchant gas. The dopant present in the gas is incorporated into the silicon defining the surfaces of the trench. This dopant is subsequently diffused to form the doped column surrounding the trench.
    Type: Grant
    Filed: February 23, 2004
    Date of Patent: March 28, 2006
    Assignee: General Semiconductor, Inc.
    Inventors: Richard A. Blanchard, Fwu-Iuan Hshieh