Abstract: Transient voltage suppressor semiconductor devices and other semiconductor devices having rigorous requirements for the diffusion and depth of impurities to produce P-N junctions can be fabricated at surprisingly low costs without sacrifice of functional characteristics by subjecting the substrate to a grinding process resulting in a surface short of polishing perfection, thereby to eliminate the time-consuming and hence costly conventional polishing operation, and then diffusing the desired impurity into the substrate from a solid impurity source.

Abstract: First and second thermoplastic case parts house a surge protector semiconductor subassembly having a plurality of components. The first and second thermoplastic case parts are substantially identical, and each case part has a semiconductor subassembly receiving recess therein. The first and second thermoplastic case parts have corresponding projections and recesses so that the first and second thermoplastic case parts may be snapped together to form a hollow case encapsulating the semiconductor subassembly. The hollow case includes spring means integral with the hollow case for applying force on the semiconductor subassembly to retain the components of the semiconductor subassembly together in the event that the case is subjected to high temperature due to a high current surge.

Abstract: In a method of injection molding elements, a first step is to charge a molding compound into an injection nozzle via a side hole defined in the nozzle under the control of a mini-plunger which is selectively reciprocally movable within a bore of the injection nozzle. In a second step, the mini-plunger is reciprocally moved in the bore of the nozzle for injecting substantially the entire molding compound in the bore of the injection nozzle into at least one cavity of a mold via a separate gate passage defined in the mold. Each gate passage is a narrow capillary aperture that connects the bore of the injection nozzle with a different one of the at least one cavity of the mold. In a third step, the nozzle and the mold are separated after the molding compound in the gate passage is cured but before the molding compound in the at least one cavity of the mold is cured. In a fourth step the molded element is removed from the at least one cavity of the mold once the molding compound therein is cured.

Abstract: The invention relates to a process for manufacturing semiconductor devices with active device structures which are connected with one another in a wafer, the area of a semiconductor device being determined by process parameters and being substantially greater than the area of an active device structure. An improvement of the process is achieved by forming several like active device structures on each of the semiconductor devices.

Abstract: To ensure bulk breakdown when the mesa diode with a positive bevel angle is reverse biased, the diffused region is formed with thinner edge portions. This eliminates corner or edge effects which create conditions of high electric field, resulting in decreased breakdown voltage and clamping voltage levels. The edges of the surface of epitaxial region are covered with a narrow oxide layer prior to diffusion. The middle portion of the surface remains uncovered. Diffusing through the oxide results in a diffused region which is thinner along the edges of the device than in the interior region below the exposed surface portion. The oxide thickness controls the depth of the edge diffusion.

Abstract: Starting with a semiconductor wafer of known type including an internal, planar p-n junction parallel to major surfaces of the wafer, one of the wafer surfaces is covered with a masking layer of silicon nitride. A plurality of intersecting grooves are then sawed through the masking layer for forming a plurality of mesas having sloped walls with each mesa including a portion of the planar p-n junction having edges which intersect and are exposed by the mesa walls. The groove walls and exposed junction edges are glass encapsulated in a process including heating the wafer. The masking layers are then removed in a selective etching process not requiring a patterned etchant mask, and the now exposed silicon surfaces at the top of the mesas, as well as the opposite surface of the wafer, are metal plated. The wafer is then diced along planes through the grooves for providing individual chips each having a glass passivated mesa thereon.

Abstract: An electroplating apparatus comprises a rotating cage with a shaft therethrough and connecting seats, each of the connecting seats being tangent to the shaft, and a plurality of containers which are respectively received in each of the connecting seats. Each of the containers comprises a thin box and a screen provided thereon as a cap, and each box includes a plurality of spaced apart baffle plates sub-dividing the box into a plurality of compartments. Each of the compartments has two side walls which are respectively provided with a plurality of thorns, so as to form two thorny walls. All electronic parts are disposed in parallel between the thorny walls to avoid entanglements and damage of parts being electroplated. Also, the thorns provide extended area electrode contacts for the parts, resulting in more uniform parts plating.