Abstract: A packet based high bandwidth copy protection method is described that includes the following operations. Forming a number of data packets at a source device, encrypting selected ones of the data packets based upon a set of encryption values, transmitting the encrypted data packets from the source device to a sink device coupled thereto, decrypting the encrypted data packets based in part upon the encryption values, and accessing the decrypted data packets by the sink device.

Abstract: A DDS circuit arranged to provide a selectable spread spectrum based output clock signal is described. The synthesizer includes a phase accumulator circuit, a reference clock source coupled to the phase accumulator circuit arranged to provide a reference clock signal, a frequency shifter unit coupled to the phase accumulator, a nominal phase source coupled to the phase accumulator coupled to the frequency shifter unit arranged to provide a nominal phase signal, and a modulated phase source coupled to the frequency shifter unit arranged to provide a modulation signal. The frequency shifter unit combines the nominal phase signal and the modulation signal to form a frequency shift signal as input to the phase accumulator which uses the frequency shift signal to sample the reference clock signal so as to produce the output clock signal having a central frequency and a frequency spread based upon the modulation signal.

Abstract: A clock recovery circuit in a digital display unit for recovering a time reference signal associated with analog display data. The clock recovery circuit includes a phase-locked loop (PLL) implemented in digital domain and an analog filter to eliminate any undesirable frequencies from the output signal of the PLL. The PLL includes independent control loops to track long term frequency drifts of the time reference signal and the transient phase differences respectively. By providing such independent control loops, the generated clock can be better synchronized with the time reference signal.

Abstract: A digital display unit for minimizing the display artifacts which may be caused by aliasing of high frequency distortions present in wide bandwidth analog display signals. The minimization is achieved by modulating a sampling clock signal by different phase delay amounts for successive lines or frame. Due to such modulation, the analog display signal is sampled at different sampling points in different frames for the same pixel position. As digital display screens are typically designed to respond slowly to differing scanning intensities and as the human eye generally averages different color intensities at the same point, a low-pass filter effect may be in place with respect to the samples taken at the same pixel position. Display artifacts are minimized due to the sampling at different sampling points and the low-pass filter effect.

Abstract: A receiver to recover data encoded at high speed in a signal over a serial communication channel. A static phase determination circuit indicates whether the signal is early, late or neutral relative to a sampling clock. The sampling clock is used to oversample the signal to generate multiple samples. A token analyzer examines the transitions around a current symbol to determine any short term phase shifts of the boundaries between symbols. The short term phase shifts and the static phase together may be used to accurately select the samples representing the symbols without requiring extensive processing.

Abstract: An automatic sampling control system for digital monitors. A clock generation circuit generates a sampling clock. A phase controller modifies the phase of the sampling clock by a phase amount. An ADC samples a frame of an analog display signal to generate digital samples. A value which is a function of the samples is generated. The function generally generates a larger value with correspondingly large sample values. The phase amount is modified for successive image frames until a maximum function value is generated. When successive image frames do not change substantially in image content, the phase amount represents the optimal phase change for the sampling clock. If the image content is changing substantially, the phase adjustment may be disabled.

Abstract: A phase comparator circuit which can compare the phase of a target clock signal with the phase of a reference clock signal with a short comparison cycle. An auxiliary waveform representative of the incremental phase of each of the reference and target clock signals may be generated, and samples on the auxiliary waveforms may be compared to determine the relative phase. The result of the comparison can be used to adjust of the phase of the target clock signal. As several samples can be taken on the auxiliary waveforms, the present invention enables frequent phase comparisons. The frequent comparisons may enable the target clock signal to be synchronized quickly with the reference clock signal. The invention has particular application in display units using phase lock loops (PLLs).

Abstract: A clock generator circuit which provides for short comparison cycles even if X and Y do not have a large common denominator when a target clock signal having a frequency of (X/Y) times the frequency of a reference clock signal is to be generated. The comparison cycle is shortened by using approximately X/L and Y/L as divisors, instead of X and Y. As X/L and/or Y/L may not equal integers, multiple divisors may be used in a weighted fashion such that the weighted averages equal X/L or Y/L as the case may be.

Abstract: A digital display unit for minimizing the display artifacts which may be caused by aliasing of high frequency distortions present in wide bandwidth analog display signals. The minimization is achieved by modulating a sampling clock signal by different phase delay amounts for successive lines or frame. Due to such modulation, the analog display signal is sampled at different sampling points in different frames for the same pixel position. As digital display screens are typically designed to respond slowly to differing scanning intensities and as the human eye generally averages different color intensities at the same point, a low-pass filter effect may be in place with respect to the samples taken at the same pixel position. Display artifacts are minimized due to the sampling at different sampling points and the low-pass filter effect.

Abstract: A display unit receiving a display signal having source image frames encoded at an encoding rate (FR.sub.S). A display screen may be refreshed at a refresh rate which is less than the encoding rate. An actual refresh rate (FR.sub.D) is determined such that FR.sub.S /FR.sub.D =(N+1)/N. To satisfy this equation, the actual refresh rate (FR.sub.D) may be selected to be slightly different from the target refresh rate supported by the display screen. Pixel data elements representing source image frames (received at FR.sub.S) may be written into a frame buffer, and the pixel data elements may be retrieved at a frequency determined by refresh rate FR.sub.D. However, at least a part of every (N+1).sup.st source image frame is not written into the frame buffer to avoid image tearing problems.

Abstract: A digital display unit receiving a display signal with image encoded at high origin frequencies (e.g., dot clock). A display signal interface samples the display signal during source display time to generate pixel data elements representative of the images encoded in the display signal. The signal is sampled at a sampling frequency equal to origin frequency. The pixel data elements are stored in a buffer at the sampling frequency and retrieved at a slower frequency. Display signals are generated for each horizontal scan line of a digital display screen during a destination display time at this slower frequency. The destination display time is designed to be longer than the source display time, which enables the display signals to be generated from all pixel data elements. The destination display time is longer than the source display time because digital display units do not require the long non-display times present in the display signals.