Abstract: A display unit designed to be scanned within a narrow horizontal scanning range irrespective of the frequency at which the horizontal lines of an image are received. If the horizontal line frequency of the received display signal does not fall within the narrow horizontal scanning range, the image frames in the display signal are scaled at least vertically such that the number of horizontal lines in each scaled image frame times the frame rate falls within the horizontal scanning range. As a result, the images can be scanned within the horizontal range for which a display unit is designed for. The scaling can be performed without using a frame buffer as the frame rate (at which the images are encoded in a display signal) equals the scanning rate.

Abstract: A digital display unit adjusting the phase of a sampling clock based on the examination of a display data signal contained in a received analog display signal. The phase may be adjusted by determining a boundary between display data portions representing successive pixel data elements. As the boundaries provide the timing information related to the source clock, the phase of the sampling clock can be adjusted when ever the boundaries can be determined accurately. The phase of the sampling clock can be adjusted potentially every sampling clock cycle if the boundaries can be determined. The area for examination can be minimized by first determining an expected boundary based on synchronization signal accompanying the analog display data, and examining only a small area surrounding the expected boundary.

Abstract: A monolithic integrated circuit for use in a digital display unit. The circuit may include an analog-to-digital converter (ADC), a scaler and a clock recovery circuit. The present invention enables the integration of at least these components into a single monolithic integrated circuit while maintaining reasonable display quality. Specifically, the monolithic integrated circuit is designed for substantial immunity from noise, which may otherwise result from integration.

Abstract: A receiver to recover data encoded at high speed in a signal over a serial communication channel. A static phase determination circuit indicates whether the signal is early, late or neutral relative to a sampling clock. The sampling clock is used to oversample the signal to generate multiple samples. A token analyzer examines the transitions around a current symbol to determine any short term phase shifts of the boundaries between symbols. The short term phase shifts and the static phase together may be used to accurately select the samples representing the symbols without requiring extensive processing.

Abstract: A clock recovery circuit in a digital display unit for recovering a time reference signal associated with analog display data. The clock recovery circuit includes a phase-locked loop (PLL) implemented in digital domain and an analog filter to eliminate any undesirable frequencies from the output signal of the PLL. The PLL includes independent control loops to track long term frequency drifts of the time reference signal and the transient phase differences respectively. By providing such independent control loops, the generated clock can be better synchronized with the time reference signal. A system and method for displaying an analog source image by a digital display unit. A converter circuit generates a plurality of digital source image elements from an analog source image based upon a sampling clock signal synchronized with a time reference signal associated with the analog source image.

Abstract: A clock recovery circuit in a digital display unit for recovering a time reference signal associated with analog display data. The clock recovery circuit includes a phase-locked loop (PLL) implemented in digital domain and an analog filter to eliminate any undesirable frequencies from the output signal of the PLL. The PLL includes independent control loops to track long term frequency drifts of the time reference signal and the transient phase differences respectively. By providing such independent control loops, the generated clock can be better synchronized with the time reference signal. Scaling a source image formed of a number of source image elements to provide a destination image formed of a number of destination image elements using a line buffer and no frame buffer.

Abstract: A clock recovery circuit in a digital display unit for recovering a time reference signal associated with analog display data. The clock recovery circuit includes a phase-locked loop (PLL) implemented in digital domain and an analog filter to eliminate any undesirable frequencies from the output signal of the PLL. The PLL includes independent control loops to track long term frequency drifts of the time reference signal and the transient phase differences respectively. By providing such independent control loops, the generated clock can be better synchronized with the time reference signal. This invention is directed to a method of scaling a source image formed of a number of source image elements to provide a destination image formed of a number of destination image elements using a line buffer and no frame buffer.