Abstract: According to some embodiments of the invention, a connector is provided for connecting any combination of an analog video source to either an analog display or a digital display or a digital video source to either an analog display or a digital display. Some preferred connectors have a serial differential digital interconnect that is pin/connector compatible with analog VGA or DB15. Some implementations of the invention provide a system and method for determining the inherent digital versus analog capability of a video source and a video display and configuring a connector according to the determination. Some implementations provide real-time display image quality assurance. Some embodiments provide a digital monitor with digital data streams having more than 8 bits per color, e.g., 10 bits or 12 bits per color.

Abstract: A method of digital image storage utilizing a number of image storage memories, utilizing separate and independent write and read controls to the storage memories, utilizing write masking to selectively write to the storage memories, utilizing full or partial read from the storage memories to simultaneously access corresponding image data from multiple images, while permitting a non-integral number of image delays between input and output.

Abstract: This invention is directed to a method and apparatus for producing video signal timing for a display device that has a display format different from the input video format. It also provides a method and apparatus for producing video signal timing in cases where the input video line rate and display output line rates are not the same. Furthermore, a method and apparatus are provided for synchronizing the display output line rate to the input line rate so that the source video line input rate can sustain the rate at which the input lines are processed to generate display video lines using a minimum amount of memory buffer for a variety of display processing methods. Another aspect of the present invention provides a method and apparatus for synchronizing display output timing to input video timing such that both are locked in terms of frame rate, but skewed in terms of frame phase, in order to accommodate latency incurred by processing of source video data to generate the display video data.