Abstract: A look ahead column redundancy circuit provides high speed memory access to both regular memory arrays and redundant memory arrays. In the preferred embodiment of the present invention, the information on both the address bus and the information on the next address bus are decoded by redundant column decoders in parallel. The decoded information from the redundant column decoders is then provided to a redundancy column pathway as the addressing information from the address bus and the next address bus is provided to a main column pathway. The information on the address bus is latched when beginning at a new column address. The information on the next address bus is latched for the next column address when operating in a burst cycle mode. The main column pathway preferably includes a latch, a main column decoder and a main column select circuit.

Abstract: An apparatus for sharing redundancy circuits between memory arrays within a semiconductor memory device includes at least two main memory arrays comprised of a plurality of memory cells aligned in rows and/or columns and a shared redundancy circuit. The redundancy circuits preferably include a plurality of redundancy rows and a redundancy decoder which is configured for accessing the redundancy rows whenever a read or write operation involves use of a defective row within the main memory arrays for which a redundant row has been substituted. Preferably, each main memory array has access to the shared redundancy circuit. The shared redundancy circuit is used for substituting defective rows within a corresponding main memory array. The shared redundancy circuit provides extra redundant capacity to both of the main memory arrays.