Patents Assigned to Genesys Testware, Inc.
  • Design-for-test techniques for a digital electronic circuit
    Patent number: 9651615
    Abstract: A digital electronic circuit (DCCT) configured for testing in accordance with a Design-for-Test (“DFT”) technique such as a hierarchical, compressed random access scan (“CRAS-N”) DFT technique and, in particular, a segmented, random access scan a (“SRAS”) DFT technique.
    Type: Grant
    Filed: July 15, 2016
    Date of Patent: May 16, 2017
    Assignee: Genesys Testware, Inc.
    Inventors: Bejoy G. Oomman, Maddumage D. G. Karunaratne
  • Design-for-test techniques for a digital electronic circuit
    Patent number: 9423455
    Abstract: A digital electronic circuit (DCCT) configured for testing in accordance with a Design-for-Test (“DFT”) technique such as a hierarchical, compressed random access scan (“CRAS-N”) DFT technique and, in particular, a segmented, random access scan a (“SRAS”) DFT technique.
    Type: Grant
    Filed: December 15, 2014
    Date of Patent: August 23, 2016
    Assignee: Genesys Testware, Inc.
    Inventors: Bejoy G. Oomman, Maddumage D. G. Karunaratne