Abstract: A cholesteric liquid crystal display (ChLCD) device comprises a ChLCD panel, a power supply module, and a system on a chip (SoC). A timing controlling software in the SoC is electrically connected to the power supply module as well as a scan driver and a data driver of the ChLCD panel. The timing controlling software configures and controls the power supply module to output a first to fourth voltage amplitude respectively from a first to fourth channel. The timing controlling software generates and outputs a voltage configuration command to the power supply module. According to the voltage configuration command and the first to the fourth voltage amplitudes, the power supply module generates a reset voltage needed across pixel electrodes for resetting the ChLCD panel and generates a display voltage needed across the pixel electrodes for displaying a frame. The ChLCD device more time efficiently refreshes the frame.

Abstract: A static image displaying method of an active matrix cholesteric liquid crystal display (AM ChLCD) is executed by a driver system for controlling the AM ChLCD. The method includes steps of: generating a voltage control command, a gate control command, and an image display command according to a static image parameter data, a data enable signal, and a vertical synchronization signal; generating a gate driver voltage and a plurality of data driver voltages according to the voltage control command; executing a set of static image display sequences for: outputting the gate driver voltage for switching on or switching off a plurality of display units of the AM ChLCD, controlling a chronological sequence of switching on or switching off the plurality of display units according to the gate control command, and outputting the plurality of data driver voltages to the plurality of display units that are switched on.

Abstract: A handwriting input image displaying method is executed by a driver system to control an active matrix cholesteric liquid crystal display (AM ChLCD). The method includes: generating a voltage control command, a gate control command, and an image display command according to a handwriting input image parameter data, a data enable signal, and a vertical synchronization signal; generating a gate driver voltage and a plurality of data driver voltages according to the voltage control command; executing a set of handwriting input image display sequences for: outputting the gate driver voltage for switching on or off a plurality of display units of the AM ChLCD, controlling a chronological sequence of switching on or off the plurality of display units according to the gate control command, and outputting the plurality of data driver voltages to the plurality of display units that are switched on, thus displaying a handwriting input image.

Abstract: A dynamic image displaying method of an active matrix cholesteric liquid crystal display (AM ChLCD) is executed by a driver system for controlling the AM ChLCD. The method includes: generating a voltage control command, a gate control command, and an image display command according to a dynamic image parameter data, a data enable signal, and a vertical synchronization signal; generating a gate driver voltage and a plurality of data driver voltages according to the voltage control command; executing a set of image display sequences for: outputting the gate driver voltage for switching on or switching off a plurality of display units of the AM ChLCD, controlling a chronological sequence of switching on or switching off the plurality of display units according to the gate control command, and outputting the plurality of data driver voltages to the plurality of display units that are switched on, thus displaying a dynamic image.

Abstract: A multistable display driven by dynamic display scheme includes a time controller circuit unit, a driver circuit unit, and a screen unit. The time controller circuit unit generates a time controller signal, and a data signal included in the time controller signal further includes a pixel dynamic display header data and a pixel dynamic display waveform data. The driver circuit unit determines a pixel display voltage value of a pixel display driver signal according to the pixel dynamic display header data. The driver circuit unit also determines a pixel display driving time duration according to the half duty count and the pixel dynamic display waveform data, and the driver circuit unit outputs the pixel display driver signal with the pixel display voltage value to the screen unit for the pixel display driving time duration. The multistable display may be driven at a low clock rate to decrease power consumption.

Abstract: The present invention provides a driving method of a cholesteric liquid crystal display (ChLCD) device, including: generating row and column driving signals respectively to the Y lines of the row circuit structures and the X lines of the column circuit structures of the ChLCD panel; wherein the row driving signals include addressing and non-addressing signals; wherein the ChLCD panel includes multiple uneven and even pixels; after the liquid crystal driving unit outputs the addressing signals to the Y-th row circuit structure, the liquid crystal driving unit outputs the non-addressing signal at least M times to the row circuit structure where the uneven pixels are located, to even out the reflectivity of the uneven pixels; and the liquid crystal driving unit outputs Hi-Z voltage signal M times to the row circuit structure of the even pixels, to maintain the reflectivity of the even pixels.

Abstract: The present invention discloses a cholesteric liquid crystal device and a driving method for partially updating an image thereof. The cholesteric liquid crystal device and the driving method partially update the color differences of a part of the pixels in the row circuit structure and maintain the color differences of the other pixels in the row circuit structure.

Abstract: A cholesteric liquid crystal display (ChLCD) device comprises a ChLCD panel, a power supply module, and a system on a chip (SoC). A timing controlling software in the SoC is electrically connected to the power supply module as well as a scan driver and a data driver of the ChLCD panel. The timing controlling software configures and controls the power supply module to output a first to fourth voltage amplitude respectively from a first to fourth channel. The timing controlling software generates and outputs a voltage configuration command to the power supply module. According to the voltage configuration command and the first to the fourth voltage amplitudes, the power supply module generates a reset voltage needed across pixel electrodes for resetting the ChLCD panel and generates a display voltage needed across the pixel electrodes for displaying a frame. The ChLCD device more time efficiently refreshes the frame.