Patents Assigned to Genitech, Inc.
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Patent number: 9702041Abstract: An apparatus and method for fabricating a semiconductor device using a 4-way valve with improved purge efficiency by improving a gas valve system by preventing dead volume from occurring are provided. The apparatus includes a reaction chamber in which a substrate is processed to fabricate a semiconductor device; a first processing gas supply pipe supplying a first processing gas into the reaction chamber; a 4-way valve having a first inlet, a second inlet, a first outlet, and a second outlet and installed at the first processing gas supply pipe such that the first inlet and the first outlet are connected to the first processing gas supply pipe; a second processing gas supply pipe connected to the second inlet of the 4-way valve to supply a second processing gas; a bypass connected to the second outlet of the 4-way valve; and a gate valve installed at the bypass.Type: GrantFiled: June 8, 2016Date of Patent: July 11, 2017Assignees: SAMSUNG ELECTRONICS CO., LTD., GENITECH, INC.Inventors: Seok-jun Won, Yong-min Yoo, Dae-youn Kim, Young-hoon Kim, Dae-jin Kwon, Weon-hong Kim
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Publication number: 20160281234Abstract: An apparatus and method for fabricating a semiconductor device using a 4-way valve with improved purge efficiency by improving a gas valve system by preventing dead volume from occurring are provided. The apparatus includes a reaction chamber in which a substrate is processed to fabricate a semiconductor device; a first processing gas supply pipe supplying a first processing gas into the reaction chamber; a 4-way valve having a first inlet, a second inlet, a first outlet, and a second outlet and installed at the first processing gas supply pipe such that the first inlet and the first outlet are connected to the first processing gas supply pipe; a second processing gas supply pipe connected to the second inlet of the 4-way valve to supply a second processing gas; a bypass connected to the second outlet of the 4-way valve; and a gate valve installed at the bypass.Type: ApplicationFiled: June 8, 2016Publication date: September 29, 2016Applicants: SAMSUNG ELECTRONICS CO., LTD., GENITECH, INC.Inventors: Seok-jun WON, Yong-min YOO, Dae-youn KIM, Young-hoon KIM, Dae-jin KWON, Weon-hong KIM
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Patent number: 9406502Abstract: An apparatus and method for fabricating a semiconductor device using a 4-way valve with improved purge efficiency by improving a gas valve system by preventing dead volume from occurring are provided. The apparatus includes a reaction chamber in which a substrate is processed to fabricate a semiconductor device; a first processing gas supply pipe supplying a first processing gas into the reaction chamber; a 4-way valve having a first inlet, a second inlet, a first outlet, and a second outlet and installed at the first processing gas supply pipe such that the first inlet and the first outlet are connected to the first processing gas supply pipe; a second processing gas supply pipe connected to the second inlet of the 4-way valve to supply a second processing gas; a bypass connected to the second outlet of the 4-way valve; and a gate valve installed at the bypass.Type: GrantFiled: April 14, 2015Date of Patent: August 2, 2016Assignees: SAMSUNG ELECTRONICS CO., LTD., GENITECH, INC.Inventors: Seok-jun Won, Yong-min Yoo, Dae-youn Kim, Young-hoon Kim, Dae-jin Kwon, Weon-hong Kim
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Publication number: 20150221497Abstract: An apparatus and method for fabricating a semiconductor device using a 4-way valve with improved purge efficiency by improving a gas valve system by preventing dead volume from occurring are provided. The apparatus includes a reaction chamber in which a substrate is processed to fabricate a semiconductor device; a first processing gas supply pipe supplying a first processing gas into the reaction chamber; a 4-way valve having a first inlet, a second inlet, a first outlet, and a second outlet and installed at the first processing gas supply pipe such that the first inlet and the first outlet are connected to the first processing gas supply pipe; a second processing gas supply pipe connected to the second inlet of the 4-way valve to supply a second processing gas; a bypass connected to the second outlet of the 4-way valve; and a gate valve installed at the bypass.Type: ApplicationFiled: April 14, 2015Publication date: August 6, 2015Applicants: GENITECH, INC., SAMSUNG ELECTRONICS CO., LTD.Inventors: Seok-jun WON, Yong-min YOO, Dae-youn KIM, Young-hoon KIM, Dae-jin KWON, Weon-hong KIM
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Patent number: 9029244Abstract: An apparatus and method for fabricating a semiconductor device using a 4-way valve with improved purge efficiency by improving a gas valve system by preventing dead volume from occurring are provided. The apparatus includes a reaction chamber in which a substrate is processed to fabricate a semiconductor device; a first processing gas supply pipe supplying a first processing gas into the reaction chamber; a 4-way valve having a first inlet, a second inlet, a first outlet, and a second outlet and installed at the first processing gas supply pipe such that the first inlet and the first outlet are connected to the first processing gas supply pipe; a second processing gas supply pipe connected to the second inlet of the 4-way valve to supply a second processing gas; a bypass connected to the second outlet of the 4-way valve; and a gate valve installed at the bypass.Type: GrantFiled: September 21, 2012Date of Patent: May 12, 2015Assignees: Samsung Electronics Co., Ltd., Genitech, Inc.Inventors: Seok-jun Won, Yong-min Yoo, Dae-youn Kim, Young-hoon Kim, Dae-jin Kwon, Weon-hong Kim
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Publication number: 20130029477Abstract: An apparatus and method for fabricating a semiconductor device using a 4-way valve with improved purge efficiency by improving a gas valve system by preventing dead volume from occurring are provided. The apparatus includes a reaction chamber in which a substrate is processed to fabricate a semiconductor device; a first processing gas supply pipe supplying a first processing gas into the reaction chamber; a 4-way valve having a first inlet, a second inlet, a first outlet, and a second outlet and installed at the first processing gas supply pipe such that the first inlet and the first outlet are connected to the first processing gas supply pipe; a second processing gas supply pipe connected to the second inlet of the 4-way valve to supply a second processing gas; a bypass connected to the second outlet of the 4-way valve; and a gate valve installed at the bypass.Type: ApplicationFiled: September 21, 2012Publication date: January 31, 2013Applicants: GENITECH, INC., SAMSUNG ELECTRONICS CO., LTD.Inventors: SAMSUNG ELECTRONICS CO., LTD., GENITECH, INC.
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Publication number: 20110097905Abstract: An apparatus and method for fabricating a semiconductor device using a 4-way valve with improved purge efficiency by improving a gas valve system by preventing dead volume from occurring are provided. The apparatus includes a reaction chamber in which a substrate is processed to fabricate a semiconductor device; a first processing gas supply pipe supplying a first processing gas into the reaction chamber; a 4-way valve having a first inlet, a second inlet, a first outlet, and a second outlet and installed at the first processing gas supply pipe such that the first inlet and the first outlet are connected to the first processing gas supply pipe; a second processing gas supply pipe connected to the second inlet of the 4-way valve to supply a second processing gas; a bypass connected to the second outlet of the 4-way valve; and a gate valve installed at the bypass.Type: ApplicationFiled: December 29, 2010Publication date: April 28, 2011Applicants: SAMSUNG ELECTRONICS CO., LTD., GENITECH, INC.Inventors: Seok-jun Won, Yong-min Yoo, Dae-youn Kim, Young-hoon Kim, Dae-jin Kwon, Weon-hong Kim
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Patent number: 6720262Abstract: A method of forming copper conductors for interconnecting active and passive elements as well as signal and power lines for circuits and devices on silicon wafers is disclosed. The method disclosed herein involves with using catalysts in conjunction with a chemical vapor deposition(CVD) process with typically using copper as a source material for forming interconnecting conductors. Interconnecting method for filling trenches, via holes, contacts, large trenches and holes for power devices and lines as well as for forming large passive elements is also disclosed. Disclosed herein are also a method of filling narrow and deep trenches and small in diameter and deep holes, and a method of forming very thin film on the flat top surface so that an etchback process, such as wet or dry etchback as well as plasma etchback processes, can be used for removing a thin film in preparation for subsequent processing steps, thereby rather expensive chemical mechanical polishing(CMP) process need not be used.Type: GrantFiled: December 15, 2000Date of Patent: April 13, 2004Assignee: Genitech, Inc.Inventors: Won Yong Koh, Hyung Sang Park, Ji Hwa Lee
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Patent number: 6645574Abstract: A noble method of forming thin films for producing semiconductor or flat panel display devices is disclosed. The method is a way of effectively forming thin films on a substrate even if reactants do not react readily in a time-divisional process gas supply sequence in a reactor by supplying reactant gases and a purge gas cyclically and sequentially in order to prevent gas-phase reactions between the reactant gases and also by generating plasma directly on a substrate synchronously with the process gas supply cycle. The method has advantages of effective thin film formation even if the reactant gases do not react readily, minimization of the purge gas supply time for reduction in process time, reduction of particle contamination during film formation process, as well as thin film formation at low temperatures.Type: GrantFiled: December 6, 2000Date of Patent: November 11, 2003Assignee: Genitech, Inc.Inventors: Chun-Soo Lee, Won-Gu Kang, Kyu-Hong Lee, Kyoung-Soo Yi
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Patent number: 6539891Abstract: A chemical deposition reactor capable of switching rapidly from one process gas to another and method of forming a thin film using the same. The reactor of the present invention comprises: a reactor cover, having an inlet and an outlet, for keeping reactant gases from other part of the reactor where the pressure is lower than inside of the reactor; a gas flow control plate, fixed onto the reactor cover, for controlling the gas flow through inlet and outlet by the spacing between itself and the reactor cover; and a substrate supporting plate for confining a reaction cell with the reactor cover. The method of the present invention can be accomplished using the above reactor. In the method, process gases including a deposition gas, a reactant gas and a purge gas are sequentially and repeatedly supplied in the reactor to form a thin film on a substrate. A RF (Radio Frequency) plasma power is applied to a plasma electrode of the reactor synchronised with the supply of at least one among the process gases.Type: GrantFiled: February 14, 2001Date of Patent: April 1, 2003Assignee: Genitech, Inc.Inventors: Chun-Soo Lee, Won-Gu Kang, Kyu-Hong Lee, Kyoung-Soo Yi
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Patent number: 6380081Abstract: A method and apparatus for vaporizing liquid source materials, where such vaporized source materials are supplied to a deposition tool such as Chemical Vapor Deposition (CVD) apparatus, and more particularly in such areas as Metalorganic Chemical Vapor Deposition (MOCVD) and Atomic Layer Deposition (ALD) applications, is disclosed. The method disclosed herein involves with increasing the temperature and the pressure of given liquid source materials to a high level of temperature and pressure states while maintaining the source materials in a liquid state, and then exposing the liquid source material instantaneously to a low pressure while maintaining the temperature of the liquid source material at the high temperature. Such sudden exposure to a low pressure makes the liquid source material vaporized, so that such vaporized source material can be supplied to such deposition tools as Metalorganic Chemical Vapor Deposition (MOCVD) and Atomic Layer Deposition (ALD) apparatus.Type: GrantFiled: November 20, 2000Date of Patent: April 30, 2002Assignee: Genitech, Inc.Inventor: Kyu Hong Lee