Abstract: A folding adaptive equalizer is provided. The equalizer comprises an equalizer core and an automatic gain control loop. The equalizing transfer function of the equalizer core is modulated by one or more gain control signals generated by the automatic gain control loop and by a folding signal generated by the automatic gain control loop. When the folding signal is inactive, an increase in the gain control signals produces an increase in the high-frequency, high-bandwidth gain of the transfer function of the equalizer core. When the folding signal is active, further gain can be applied by decreasing the gain control signals, which produces a frequency-shift in the transfer function of the equalizer core toward lower bandwidth and an increase in the high-frequency, low-bandwidth gain of the transfer function of the equalizer core.

Abstract: Systems and methods are provided herein for interfacing a first digital device with a second digital device. An exemplary method includes the steps of combining one of a plurality of digital content channels and a back channel to form a composite channel, the back channel for transmitting information from the second multi-media digital device to the first multi-media digital device, converting a digital content channel and the composite channel from the first digital device into a plurality of single-ended digital content channels, transporting the plurality of single-ended digital content channels from the first digital device to the second digital device, and converting the single-ended digital content channels back into the digital content channel and the composite channel that are supplied to the second digital device. Cross-talk interference is reduced between the back channel and one of the plurality of digital content channels via a cross-talk cancellation filter.

Abstract: A direct attach optical receiver module and a system and method for testing the direct attach optical receiver module are provided. An optical receiver module may include an optical detector and an integrated circuit with an integrated amplifier circuit and at least one integrated capacitor. In one example, the optical detector may be physically attached to the integrated circuit and the output port of the optical detector may be electrically coupled to the input port of the integrated circuit. In another example, a redistribution layer that includes a tuning inductor may be being physically attached between the optical detector and the integrated circuit.

Abstract: Systems and methods are provided for reducing pathological conditions in a serial video interface. A sequence of parallel data words that are to be transformed by a data-scrambling algorithm comprise an input signal. The bit order of one or more of the words in the sequence of parallel data words is reversed and the sequence of parallel data words, now including one or more bit-reversed words, is transmitted. The signal resulting from application of a data-scrambling algorithm to the sequence of parallel data words, including one or more bit-reversed words, has a reduced likelihood of including a pathological condition.

Abstract: A crosspoint selector switch and test module, comprising: a crosspoint switch having a plurality of inputs and a plurality of outputs, wherein the outputs can be selectively switched to respective inputs; and a test system co-packaged with the crosspoint switch, the test system comprising a test signal generator that can be selectively connected to provide signals to the inputs of the crosspoint switch and a test signal analyzer that can be selectively connected to receive signals from the outputs of the crosspoint switch, wherein the test signal generator is configured to produce video data test signals that conform to a known format, and the signal analyzer is configured to analyze video data test signals that conform to the known format.

Abstract: A crosspoint selector switch for simultaneously supporting multiple data formats having different switch reconfiguration timing requirements, comprising; a configurable switch section for selectively connecting outputs thereof to receive data from respective inputs thereof in response to operational switch data; and a configuration section operatively connected to provide the operational switch data to the switch section, the configuration section storing switch configuration data supporting multiple different configurations of the switch section, the configuration section being operative to receive different operational update commands each associated with a different configuration for the switch section and update the operational switch data from the stored switch configuration data to reconfigure the switch section in dependence on which of the different operational update commands is received.

Abstract: An adaptive equalizer may include one or more equalizing gain stages coupled to an input signal. An automatic gain control circuit may be used to control the gain of the one or more equalizing gain stages, the automatic gain control circuit having an AGC reference input. A dual-output DC restoration circuit may be coupled to the output of the one or more equalizing gain stages for generating a first output signal using a first hysteresis slicer that DC restores the input signal and for generating a second output signal using a second hysteresis slicer that is coupled to the AGC reference input of the automatic gain control circuit, wherein the second hysteresis slicer introducing less hysteresis than the first hysteresis slicer.

Abstract: In accordance with the teachings described herein, an extended equalizer circuit is provided for equalizing a digital communication signal transmitted over a transmission medium that causes a frequency-dependent attenuation of the digital communication signal. An equalizer may be used that includes a linear equalization circuit and a non-linear equalization circuit, the linear equalization circuit being configured to apply a linear filter to the digital communication signal to compensate for the frequency-dependent attenuation caused by a first portion of the transmission medium, and the non-linear equalization circuit being configured to apply one or more non-linear operations to the digital communication signal.

Abstract: A method for converting data received in either a Level A or Level B SMPTE 425M compliant format into either a Level B or a Level A compliant format, respectively, includes receiving and processing data in one of a Level A or a Level B SMPTE 425M compliant format. Inputting the received Level A formatted data into a storage device and reading out Level B formatted data at an output of the storage device, or inputting Level B formatted data into the storage device and reading out Level A formatted data at an output of the storage device. Back-end circuitry further processes the Level A formatted data when Level B formatted data is received or further processes the Level B formatted data when Level A formatted data is received. The storage device is operated as a line multiplexer to convert data in a Level B format to data in a Level A format and is operated as a line demultiplexer to convert data in a Level A format to data in a Level B format.

Abstract: A direct attach optical receiver module and a system and method for testing the direct attach optical receiver module are provided. An optical receiver module may include an optical detector and an integrated circuit with an integrated amplifier circuit and at least one integrated capacitor. In one example, the optical detector may be physically attached to the integrated circuit and the output port of the optical detector may be electrically coupled to the input port of the integrated circuit. In another example, a redistribution layer that includes a tuning inductor may be being physically attached between the optical detector and the integrated circuit.

Abstract: A direct attach optical receiver module and a system and method for testing the direct attach optical receiver module are provided. An optical receiver module may include an optical detector and an integrated circuit with an integrated amplifier circuit and at least one integrated capacitor. In one example, the optical detector may be physically attached to the integrated circuit and the output port of the optical detector may be electrically coupled to the input port of the integrated circuit. In another example, a redistribution layer that includes a tuning inductor may be being physically attached between the optical detector and the integrated circuit.

Abstract: Linear sample and hold phase detectors are disclosed herein. An example phase detector is coupled to an input data signal and a recovered clock signal and includes a linear phase difference generator circuit and a sample and hold circuit. The linear phase difference generator includes a first input coupled to the input data signal and a second input coupled to the recovered clock signal and outputs a first phase difference signal indicative of the phase difference between the input data signal and the recovered clock signal relative to a rising edge of the input data signal and a second phase difference signal indicative of the phase difference between the input data signal and the recovered clock signal relative to a falling edge of the input data signal.

Abstract: A digital communication system for transmitting and receiving video data signals and control data signals over a transmission line comprises an open-loop equalizer circuit and a control data extension circuit. The open-loop equalizer circuit is operable to receive video signals transmitted over the transmission line and output equalized video data signals. The control data extension circuit is operable to inject a boost current at the receive end of the transmission line during a positive transition in the control data signal, and clamp the receive end of the transmission line during a negative transition of the control data signal.

Abstract: A folding adaptive equalizer is provided. The equalizer comprises an equalizer core and an automatic gain control loop. The equalizing transfer function of the equalizer core is modulated by one or more gain control signals generated by the automatic gain control loop and by a folding signal generated by the automatic gain control loop. When the folding signal is inactive, an increase in the gain control signals produces an increase in the high-frequency, high-bandwidth gain of the transfer function of the equalizer core. When the folding signal is active, further gain can be applied by decreasing the gain control signals, which produces a frequency-shift in the transfer function of the equalizer core toward lower bandwidth and an increase in the high-frequency, low-bandwidth gain of the transfer function of the equalizer core.

Abstract: In accordance with the teachings described herein, systems and methods are provided for a precision adaptive equalizer. A variable gain equalizer may be used to apply a variable gain to an input signal to generate an equalized output signal. A phase and pattern detector circuit may be coupled in a feedback loop with the variable gain equalizer. The phase and pattern detector circuit may be used to identify a high frequency data pattern in the equalized output signal and compare the high frequency data pattern with a clock signal to detect a high frequency phase error. The phase and pattern detector circuit may be further operable to generate an automatic gain control signal as a function of the high frequency phase error, the automatic gain control signal being fed back to the variable gain equalizer to control the variable gain applied to the input signal.

Abstract: Systems and methods are provided for depositing solder in a first pattern over a first bonding pad on the substrate; depositing solder in a second pattern over a second bonding pad on the substrate, wherein the second pattern defines a larger area than the first pattern; placing the electronic device on the substrate such that pads on the electronic device are aligned with the first and second bonding pads; and reflowing the solder between the pads on the electronic device and the first and second bonding pads, causing the solder deposited on the first bonding pad to form a first solder joint and the solder deposited on the second bonding pad to form a second solder joint. The second solder joint is larger than the first solder joint causing the electronic device to be attached at an angle relative to the substrate.

Abstract: Transmit amplitude independent adaptive equalizers are provided that compensate for transmission losses in an input signal when the transmit signal amplitude is unknown. Several embodiments are provided, including a first embodiment having an equalizer core, a controllable-swing slicer and an amplitude control loop, a second embodiment having an equalizer core, a fixed-swing slicer and a control loop, a third embodiment having an equalizer core, a variable gain amplifier, and a variable gain amplifier control loop, and a fourth embodiment having an equalizer core, a fixed-swing slicer, a variable gain amplifier, and a variable gain amplifier control loop.

Abstract: An extender circuit for handling a communication signal transmitted over a transmission line includes a voltage clamp and a current booster circuit. The voltage clamp is connected to a receive end of the transmission line and is operable to clamp a reflection signal caused by the communication signal received at the receive end of the transmission line. The current booster circuit is connected to the receive end of the transmission line and is operable to provide a boost current at the receive end of the transmission line during a positive transition of the communication signal.

Abstract: A direct attach optical receiver module and a system and method for testing the direct attach optical receiver module are provided. An optical receiver module may include an optical detector and an integrated circuit with an integrated amplifier circuit and at least one integrated capacitor. In one example, the optical detector may be physically attached to the integrated circuit and the output port of the optical detector may be electrically coupled to the input port of the integrated circuit. In another example, a redistribution layer that includes a tuning inductor may be being physically attached between the optical detector and the integrated circuit.

Abstract: A digital communication system for transmitting and receiving Digital Visual Interface (DVI) communication data signals and Display Data Channel (DDC) communication signals over a transmission line comprises an open-loop equalizer circuit and a DDC extension circuit. The open-loop equalizer circuit is operable to receive DVI communication signals transmitted over the transmission line and output equalized DVI communication data signals. The DDC extension circuit is operable to inject a boost current at the receive end of the transmission line during a positive transition in the DDC communication signal, and clamp the receive end of the transmission line during a negative transition of the DDC communication signal.