Abstract: A tester (10) for testing an electronic circuit (22) has test terminals (18a-d) that are to be connected to the terminals (20a-d) of the circuit under test. The tester terminals (18a-d) are placed in the states required for testing by formatter circuits (32a-d) in accordance with state codes generated by state-code generators (24a-d). However, the state-code generators (24a-d) are not required to generate every code as quickly as those codes are needed by the formatters (32a-d), because first-in, first-out memory stacks (30a-d) are interposed between the state-code generators (24a-d) and the formatters (32a-d). This permits the state-code generators (24a-d) to employ relatively slow--and thus relatively inexpensive--memories (26).

Abstract: An error-detection circuit (10) employs comparison circuitry (12) to determine whether a SENSE signal is within a range indicated by XPRANGE signals. When the SENSE signal goes into or out of the indicated range, an INRANGE output of the comparison circuitry (12) moves through a predetermined voltage swing from one stable level through a threshold level to another stable level. The passage of the INRANGE signal through the threshold level is an indication to subsequent circuitry that SENSE has passed into or out of the indicated range. According to the present invention, one or other of the levels occupied by the INRANGE signal is separated from the threshold by a voltage that is only a small fraction of the swing between the two levels. As a consequence, the delay between the transition of the SENSE signal and the transition of the INRANGE output of the comparison circuitry is only a small fraction of the time required to complete the voltage swing.

Abstract: A driver-sensor circuit for a circuit-testing device has a sensor amplifier (Q1, Q2, Q3, and Q4) for sensing the voltage on a device under test connected to its input-output terminal (12). The driver-sensor circuit also includes a driver amplifier (Q5, Q6, Q7, and Q8) for driving the same terminal (12). The driver amplifier (Q5, Q6, Q7, and Q8) can be switched on and off, and a limiting amplifier (Q9, Q10, Q11, and Q12) applies the sensor-amplifier output voltage to the input terminal (20) of the driver circuit (Q5, Q6, Q7, and Q8) to keep the reverse bias on the driver-amplifier transistors (Q5, Q6, Q7, and Q8) to a minimum. To eliminate offset bias current at the input terminal 12 of the sense amplifier (Q1, Q2, Q3, and Q4), compensation transistors (Q15, Q16 ) matching the input-stage transistors (Q1, Q2) of the driver amplifier have their bases tied together to force their base currents to cancel.

Abstract: A microprocessor-based system (10) is tested by a testing device (32) that substitutes instructions from a substitute memory (38) for those in the main memory (28) of the system (10) under test. When the processor (12) of the system under test attempts to read a location in its memory (28), it places signals on bus address lines (22) to designate the memory location and places a data-direction signal on a control line (50) to indicate that the memory (28) is to transmit rather than receive information. In ordinary operation, the memory then places its data on bus data lines (24). In order to replace the data from the main memory (28) with data from the substitute memory (38), the testing device (32) senses whether the address lines (22) carry the address of a memory location whose contents are to be substituted. When such an address is detected, it overdrives the control line (50) to cause it to indicate a write rather than a read.

Abstract: This disclosure is concerned with suppressing spurious signals generated during the in-circuit testing of circuit components, and which spurious signals may interfere with test signals being forced at selected nodes of the circuit that are inputs to components being tested and wherein such spurious signals may be routed via certain of the other circuit components, by automatically inhibiting either potential transmission of spurious signals by applying specific signals to components identified by analysis as normally feeding or processing input signals to the component(s) under test, or automatically inhibiting all inhibitable input parts of all components identified as those capable of passing such spurious signals to the input of the component(s) under test.

Abstract: This apparatus controls the execution and content of computer programs in equipment containing a computer by causing the transfer of program data elements, including computer instructions, with a memory of the apparatus. The selection of data for transfer is effected either by the computer, operating in a normal manner, or by the apparatus, which may shift data selection between these two selection options so that the computer ceases selection of data constituting one program and begins selecting data of another program. While data elements are being transferred with the computer, other elements of the memory are available for examination and modification such that new programs, the content of which may depend on the results of prior program execution, can be loaded, executed, and examined without interrupting, delaying, halting, or otherwise disturbing the instruction flow of the computer equipment.

Abstract: A DC amplifier uses complementary npn and pnp output transistors on n-type and p-type substrates, respectively. The output transistors are in an emitter-follower configuration with no emitter resistor to prevent thermal runaway. Instead, emitter-follower driver-stage transistors are provided on the same substrates as the output transistors to force a reduction in the bias voltage on the output stage when the temperature of an output transistor increases. This circuit prevents thermal runaway and temperature-dependent offsets without emitter resistors, which would increase output impedance, and without feedback from the output stage to the input stage, which would slow the response of the amplifier. Additionally, compensation-network transistors are provided to eliminate offsets resulting from driver- and output-transistor base-to-emitter voltage differences caused not only by temperature differences between the transistors on different substrates but also by manufacturing variations.

Abstract: A foldback power supply (12) is used in an automatic testing device for application of power to a device under test (17). Connection to the device under test is made by means of relay contacts (32, 34, 36, and 38). Arcing and unacceptable transients are avoided by means of a current sink (40) in parallel with the power supply (20). The current sink is operated to draw more than the rated current of the power supply so that the power-supply voltage drops to an acceptable level and the stored energy is simultaneously dissipated. The relay contacts (32, 34, 36, and 38) can then be opened or closed without unacceptably large transients and without the time delays that might otherwise be encountered in waiting for energy dissipation of the energy in the energy-storage elements of the power supply (12) and the device under test (17).

Abstract: This disclosure is concerned with the automatic diagnosis of the failure of tri-state, two-state and other electrical or electronic devices or components connected to common bus nodes through the pulling of such nodes to high or low voltage state levels during the disabling of all devices connected to the common bus node(s) in order to determine if a failed device is interfering with the normal bus operation; and if so, to proceed automatically to compare parametric measurements of the failed common bus node(s) with purposefully failed selected devices, one by one, to locate the device interfering with the normal bus operation.

Abstract: A field maintenance processor including a microprocessor that effects transparent refreshing of a dynamic memory includes a counter circuit which times the duration of the "wait" signal produced by a slow memory or a slow peripheral device accessed by the processor. The counter circuit produces a "wait enable" signal which enables the "wait" signal to produce an "enabled wait" signal that is conducted to a wait input of the processor for only a predetermined time, to ensure transparent refreshing of the entire dynamic memory. If the "wait" signal produced by the slow memory device has not ceased when the predetermined time has elapsed, the "wait enable" signal disappears, causing the "enabled wait" signal also to disappear. The disappearance of the "wait enable" signal also causes a "wait interrupt" signal to be generated and transmitted to the microprocessor, resulting in execution of an interrupt routine to determine which instruction execution was earlier halted in response to the "enabled wait" signal.

Abstract: This disclosure is concerned with a process for connecting a short detector to electrical nodes in such apparatus as backplanes, cables, and circuit boards, before and after component assembly, to identify shorted node pairs in a substantially smaller number of tests than required by previously known methods, through a novel series of tests between each node and all other nodes, taken together, so as to identify shorted nodes, and then a series of tests between each of these shorted nodes and all other shorted nodes, taken individually, to identify the shorted node pairs.

Abstract: This disclosure is concerned with a new technique for automatically measuring impedance (though the process is also applicable to other parameters and characteristics as well) wherein a series of voltages are sequentially presented to a common detector and analog-to-digital converter, the numerical values of which voltages are of themselves meaningless, but from which, with the aid of microprocessor calculating equipment, ratios may be calculated that indicate impedance (or other parameters).

Abstract: A high speed print head system includes a print head pivotally and resiliently coupled to a frame which is laterally movable on a carriage system. The print head includes an elongated nose piece having therein a plurality of print rods which can be controllably forced beyond the end of the nose piece to impact a ribbon and paper supported by a platen to produce dots on the paper. The pivotal and resilient coupling is achieved by means of a flexure having first and second opposed connection points connected to the frame and third and fourth opposed connection points connected to the print head. Two permanent magnets are rigidly attached to the frame substantially above the axis of the elongated nose piece and substantially symmetrically with respect to the elongated nose piece. A pair of electromagnets rigidly attached to the print head opposite the respective permanent magnets are controllably energized to produce continuously variable forces between the frame and the print head.

Abstract: This disclosure is concerned with a process for connecting a short detector to electrical nodes in such apparatus as backplanes, cables and circuit boards before components are assembled thereto, to identify shorted node pairs in a substantially smaller number of tests than required by previously known methods, through a novel binary screening and then binary searching technique; the invention being especially efficient in the case where no shorts are present.

Abstract: This disclosure is concerned with a novel method and apparatus peripherally and interactively used with automatic fault detecting computer systems and the like, wherein external control is provided for introducing intelligence into the probing of circuit board nodes and the like where insights into predictable or likely failures are available and the over-riding or discontinuing of normal computer-guided time-consuming back-tracking probing is thus desirable.

Abstract: This disclosure is concerned with a novel front-end circuit for impedance measuring circuits and the like, involving separately or alternately operated grounding switches for connecting the free terminals of unknown and standard impedances, series-connected at a common terminal, to ground, for enabling separate selected voltage measurements between the unknown and standard, and with the series-connected impedances fed from a floating transformer; the circuit avoiding errors due to low switch impedances and obviating dependence upon capacitance from either side of the unknown impedance to ground and upon the series impedance involved in connections or leads to the unknown impedance.

Abstract: A method and apparatus are disclosed for identifying and locating faults in the portion of circuit assemblies containing digital signals by conducting in-circuit tests embodying the application of uninterrupted sequences of signals to nodes of the circuits and the comparison of nodal signals to expected values, reducing the complex testing of the circuit assemblies to a series of simple tests of components or groups of components constituting the assemblies; and, in connection with bus-structured circuits, eliminating the possibility of bus contention problems in good circuit assemblies under test.

Abstract: This disclosure is concerned with the use of on-line simulation of circuit faults during diagnosis to generate a small part of a complete fault dictionary needed for diagnosis of the circuit, being adapted for use of a mini-computer-based automated test system having only a small amount of secondary storage; and being adapted for an exact match diagnosis with modeled failures, and a heuristic approach for a partial match of faulty behaviour that leads to a highly probable diagnosis.

Abstract: This disclosure is concerned with a new technique for automatically measuring impedance (though the process is also applicable to other parameters and characteristics as well) wherein a series of voltages are sequentially presented to a common detector and analog-to-digital converter, the numerical values of which voltages are of themselves meaningless, but from which, with the aid of microprocessor calculating equipment, ratios may be calculated that indicate impedance (or other parameters).

Abstract: This disclosure is concerned with novel current-tracing of short circuits in printed circuit boards and similar systems by novel test excitation of the conductors with tracing of the phase polarities of the fields generated therein.